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Message-ID: <20240201210529.7728-11-quic_c_gdjako@quicinc.com>
Date: Thu, 1 Feb 2024 13:05:29 -0800
From: Georgi Djakov <quic_c_gdjako@...cinc.com>
To: <robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
<conor+dt@...nel.org>, <will@...nel.org>, <robin.murphy@....com>,
<joro@...tes.org>, <iommu@...ts.linux.dev>
CC: <devicetree@...r.kernel.org>, <andersson@...nel.org>,
<konrad.dybcio@...aro.org>, <robdclark@...il.com>,
<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-msm@...r.kernel.org>, <quic_cgoldswo@...cinc.com>,
<quic_sukadev@...cinc.com>, <quic_pdaly@...cinc.com>,
<quic_sudaraja@...cinc.com>, <djakov@...nel.org>
Subject: [PATCH v4 10/10] arm64: dts: qcom: sc7280: Add DT nodes for the TBUs
Add the device-tree nodes for the TBUs (translation buffer units) that
are present on the sc7280 platforms. The TBUs can be used debug the
kernel and provide additional information when a context faults occur.
Describe the all registers, clocks, interconnects and power-domain
resources that are needed for each of the TBUs.
Signed-off-by: Georgi Djakov <quic_c_gdjako@...cinc.com>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 97 ++++++++++++++++++++++++++++
1 file changed, 97 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index c3a94c4c6490..9fbba9d7b090 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2881,6 +2881,7 @@ adreno_smmu: iommu@...0000 {
compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu",
"qcom,smmu-500", "arm,mmu-500";
reg = <0 0x03da0000 0 0x20000>;
+ ranges;
#iommu-cells = <2>;
#global-interrupts = <2>;
interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
@@ -2913,6 +2914,21 @@ adreno_smmu: iommu@...0000 {
power-domains = <&gpucc GPU_CC_CX_GDSC>;
dma-coherent;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ gfx_0_tbu: tbu@...9000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x0 0x3dd9000 0x0 0x1000>;
+ stream-id-range = <0x0 0x400>;
+ };
+
+ gfx_1_tbu: tbu@...d000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x0 0x3ddd000 0x0 0x1000>;
+ stream-id-range = <0x400 0x400>;
+ };
};
remoteproc_mpss: remoteproc@...0000 {
@@ -5637,6 +5653,7 @@ pil-reloc@...c {
apps_smmu: iommu@...00000 {
compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
reg = <0 0x15000000 0 0x100000>;
+ ranges;
#iommu-cells = <2>;
#global-interrupts = <1>;
dma-coherent;
@@ -5721,6 +5738,86 @@ apps_smmu: iommu@...00000 {
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ anoc_1_tbu: tbu@...dd000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x0 0x151dd000 0x0 0x1000>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>;
+ stream-id-range = <0x0 0x400>;
+ };
+
+ anoc_2_tbu: tbu@...e1000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x0 0x151e1000 0x0 0x1000>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>;
+ stream-id-range = <0x400 0x400>;
+ };
+
+ mnoc_hf_0_tbu: tbu@...e5000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x0 0x151e5000 0x0 0x1000>;
+ interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC>;
+ stream-id-range = <0x800 0x400>;
+ };
+
+ mnoc_hf_1_tbu: tbu@...e9000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x0 0x151e9000 0x0 0x1000>;
+ interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC>;
+ stream-id-range = <0xc00 0x400>;
+ };
+
+ compute_dsp_0_tbu: tbu@...ed000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x0 0x151ed000 0x0 0x1000>;
+ interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU1_GDSC>;
+ stream-id-range = <0x1000 0x400>;
+ };
+
+ compute_dsp_1_tbu: tbu@...f1000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x0 0x151f1000 0x0 0x1000>;
+ interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC>;
+ stream-id-range = <0x1400 0x400>;
+ };
+
+ adsp_tbu: tbu@...f5000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x0 0x151f5000 0x0 0x1000>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &lpass_ag_noc SLAVE_LPASS_CORE_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ stream-id-range = <0x1800 0x400>;
+ };
+
+ anoc_1_pcie_tbu: tbu@...f9000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x0 0x151f9000 0x0 0x1000>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>;
+ stream-id-range = <0x1c00 0x400>;
+ };
+
+ mnoc_sf_0_tbu: tbu@...fd000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x0 0x151fd000 0x0 0x1000>;
+ interconnects = <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
+ power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC>;
+ stream-id-range = <0x2000 0x400>;
+ };
};
intc: interrupt-controller@...00000 {
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