linux-kernel - Re: [PATCH v6 11/15] MIPS: mobileye: Add EyeQ5 dtsi

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Message-ID: <32ac8056-1820-4871-8526-8b467162d78e@linaro.org>
Date: Thu, 1 Feb 2024 10:14:19 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Gregory CLEMENT <gregory.clement@...tlin.com>,
 Paul Burton <paulburton@...nel.org>,
 Thomas Bogendoerfer <tsbogend@...ha.franken.de>, linux-mips@...r.kernel.org,
 Jiaxun Yang <jiaxun.yang@...goat.com>, Rob Herring <robh+dt@...nel.org>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Cc: Vladimir Kondratiev <vladimir.kondratiev@...ileye.com>,
 Tawfik Bayouk <tawfik.bayouk@...ileye.com>,
 Alexandre Belloni <alexandre.belloni@...tlin.com>,
 Théo Lebrun <theo.lebrun@...tlin.com>,
 Thomas Petazzoni <thomas.petazzoni@...tlin.com>
Subject: Re: [PATCH v6 11/15] MIPS: mobileye: Add EyeQ5 dtsi

On 18/01/2024 16:52, Gregory CLEMENT wrote:
> Add a device tree include file for the Mobileye EyeQ5 SoC.
> 
> Based on the work of Slava Samsonov <stanislav.samsonov@...el.com>
> 
> Signed-off-by: Gregory CLEMENT <gregory.clement@...tlin.com>
> ---

..

> +
> +	soc: soc {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +		compatible = "simple-bus";
> +
> +		uart0: serial@...000 {
> +			compatible = "arm,pl011", "arm,primecell";
> +			reg = <0 0x800000 0x0 0x1000>;
> +			reg-io-width = <4>;
> +			interrupt-parent = <&gic>;
> +			interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks  = <&uart_clk>, <&occ_periph>;
> +			clock-names = "uartclk", "apb_pclk";
> +		};
> +
> +		uart1: serial@...000 {
> +			compatible = "arm,pl011", "arm,primecell";
> +			reg = <0 0x900000 0x0 0x1000>;
> +			reg-io-width = <4>;
> +			interrupt-parent = <&gic>;
> +			interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks  = <&uart_clk>, <&occ_periph>;
> +			clock-names = "uartclk", "apb_pclk";
> +		};
> +
> +		uart2: serial@...000 {
> +			compatible = "arm,pl011", "arm,primecell";
> +			reg = <0 0xa00000 0x0 0x1000>;
> +			reg-io-width = <4>;
> +			interrupt-parent = <&gic>;
> +			interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks  = <&uart_clk>, <&occ_periph>;
> +			clock-names = "uartclk", "apb_pclk";
> +		};
> +
> +		olb: olb@...000 {

That's not a correct name. Please do not send knowingly incorrect DTS.

> +			compatible = "mobileye,eyeq5-olb", "syscon", "simple-mfd";
> +			reg = <0 0xe00000 0x0 0x400>;
> +			reg-io-width = <4>;

That's not needed property here.

> +		};
> +
> +		gic: interrupt-controller@...000 {
> +			compatible = "mti,gic";
> +			reg = <0x0 0x140000 0x0 0x20000>;
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +
> +			/*
> +			* Declare the interrupt-parent even though the mti,gic
> +			* binding doesn't require it, such that the kernel can
> +			* figure out that cpu_intc is the root interrupt
> +			* controller & should be probed first.
> +			*/
> +			interrupt-parent = <&cpu_intc>;
> +
> +			timer {
> +				compatible = "mti,gic-timer";
> +				interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
> +				clocks = <&core0_clk>;
> +			};
> +		};
> +	};
> +};
> +

Stray blank line.

Best regards,
Krzysztof