linux-kernel - Re: [PATCH] drm/msm/dpu: fix the programming of INTF_CFG2_DATA_HCTL

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Message-ID: <45ddbe67-2803-1a33-ceb7-3411229a59f2@quicinc.com>
Date: Wed, 31 Jan 2024 17:11:42 -0800
From: Abhinav Kumar <quic_abhinavk@...cinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
CC: <freedreno@...ts.freedesktop.org>, Rob Clark <robdclark@...il.com>,
        "Sean
 Paul" <sean@...rly.run>,
        Marijn Suijten <marijn.suijten@...ainline.org>,
        "David Airlie" <airlied@...il.com>, Daniel Vetter <daniel@...ll.ch>,
        Stephen
 Boyd <swboyd@...omium.org>,
        Kuogee Hsieh <quic_khsieh@...cinc.com>,
        <dri-devel@...ts.freedesktop.org>, <seanpaul@...omium.org>,
        <quic_jesszhan@...cinc.com>, <quic_parellan@...cinc.com>,
        <linux-arm-msm@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] drm/msm/dpu: fix the programming of
 INTF_CFG2_DATA_HCTL_EN



On 1/31/2024 5:05 PM, Dmitry Baryshkov wrote:
> On Thu, 1 Feb 2024 at 02:48, Abhinav Kumar <quic_abhinavk@...cinc.com> wrote:
>>
>> Currently INTF_CFG2_DATA_HCTL_EN is coupled with the enablement
>> of widebus but this is incorrect because we should be enabling
>> this bit independent of widebus except for cases where compression
>> is enabled in one pixel per clock mode.
>>
>> Fix this by making the condition checks more explicit and enabling
>> INTF_CFG2_DATA_HCTL_EN for all other cases when supported by DPU.
>>
>> Fixes: 3309a7563971 ("drm/msm/dpu: revise timing engine programming to support widebus feature")
>> Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
>> Signed-off-by: Abhinav Kumar <quic_abhinavk@...cinc.com>
> 
> Thank you!
> 
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
> 
> For the reference: although it is marked as a fix, I'd prefer if this
> patch undergoes a full cycle through msm-next rather than
> fast-tracking through msm-fixes. This would allow us to catch possible
> issues. WDYT?
> 

Yes, I dont plan to take this in -fixes.

Even though this was tested with sc7280, sm8550 before posting, I would 
like to postpone it for a major release as no use-case other than YUV420 
is broken without this.

This will be taken as part of CDM over DP series as we will backout the 
other change: https://patchwork.freedesktop.org/patch/575963/

>> ---
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c       |  7 +++++++
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h       |  7 +++++++
>>   .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c  |  1 +
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c       | 15 +++++++++------
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h       |  1 +
>>   5 files changed, 25 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> index 83380bc92a00..467f874979d5 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> @@ -230,6 +230,13 @@ bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc)
>>          return dpu_enc->wide_bus_en;
>>   }
>>
>> +bool dpu_encoder_is_dsc_enabled(const struct drm_encoder *drm_enc)
>> +{
>> +       const struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
>> +
>> +       return dpu_enc->dsc ? true : false;
>> +}
>> +
>>   int dpu_encoder_get_crc_values_cnt(const struct drm_encoder *drm_enc)
>>   {
>>          struct dpu_encoder_virt *dpu_enc;
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
>> index 4c05fd5e9ed1..fe6b1d312a74 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
>> @@ -158,6 +158,13 @@ int dpu_encoder_get_vsync_count(struct drm_encoder *drm_enc);
>>
>>   bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc);
>>
>> +/**
>> + * dpu_encoder_is_dsc_enabled - indicate whether dsc is enabled
>> + *                             for the encoder.
>> + * @drm_enc:    Pointer to previously created drm encoder structure
>> + */
>> +bool dpu_encoder_is_dsc_enabled(const struct drm_encoder *drm_enc);
>> +
>>   /**
>>    * dpu_encoder_get_crc_values_cnt - get number of physical encoders contained
>>    *     in virtual encoder that can collect CRC values
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
>> index d0f56c5c4cce..f562beb6f797 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
>> @@ -102,6 +102,7 @@ static void drm_mode_to_intf_timing_params(
>>          }
>>
>>          timing->wide_bus_en = dpu_encoder_is_widebus_enabled(phys_enc->parent);
>> +       timing->compression_en = dpu_encoder_is_dsc_enabled(phys_enc->parent);
>>
>>          /*
>>           * for DP, divide the horizonal parameters by 2 when
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
>> index 6bba531d6dc4..965692ef7892 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
>> @@ -163,13 +163,8 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
>>          hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width;
>>          display_hctl = (hsync_end_x << 16) | hsync_start_x;
>>
>> -       /*
>> -        * DATA_HCTL_EN controls data timing which can be different from
>> -        * video timing. It is recommended to enable it for all cases, except
>> -        * if compression is enabled in 1 pixel per clock mode
>> -        */
>>          if (p->wide_bus_en)
>> -               intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN | INTF_CFG2_DATA_HCTL_EN;
>> +               intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN;
>>
>>          data_width = p->width;
>>
>> @@ -229,6 +224,14 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
>>          DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg);
>>          DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format);
>>          if (ctx->cap->features & BIT(DPU_DATA_HCTL_EN)) {
>> +               /*
>> +                * DATA_HCTL_EN controls data timing which can be different from
>> +                * video timing. It is recommended to enable it for all cases, except
>> +                * if compression is enabled in 1 pixel per clock mode
>> +                */
>> +               if (!(p->compression_en && !p->wide_bus_en))
>> +                       intf_cfg2 |= INTF_CFG2_DATA_HCTL_EN;
>> +
>>                  DPU_REG_WRITE(c, INTF_CONFIG2, intf_cfg2);
>>                  DPU_REG_WRITE(c, INTF_DISPLAY_DATA_HCTL, display_data_hctl);
>>                  DPU_REG_WRITE(c, INTF_ACTIVE_DATA_HCTL, active_data_hctl);
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
>> index 0bd57a32144a..6f4c87244f94 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
>> @@ -33,6 +33,7 @@ struct dpu_hw_intf_timing_params {
>>          u32 hsync_skew;
>>
>>          bool wide_bus_en;
>> +       bool compression_en;
>>   };
>>
>>   struct dpu_hw_intf_prog_fetch {
>> --
>> 2.40.1
>>
> 
>