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Date: Thu, 1 Feb 2024 20:31:10 -0800
From: Elliot Berman <quic_eberman@...cinc.com>
To: Charlie Jenkins <charlie@...osinc.com>
CC: Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt
<palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>, Jisheng Zhang
<jszhang@...nel.org>,
Evan Green <evan@...osinc.com>,
Clément Léger <cleger@...osinc.com>,
<linux-riscv@...ts.infradead.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 2/2] riscv: Disable misaligned access probe when
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
Hi Charlie,
On Thu, Feb 01, 2024 at 03:30:46PM -0800, Charlie Jenkins wrote:
> When CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is selected, the cpus can be
> set to have fast misaligned access without needing to probe.
>
> Signed-off-by: Charlie Jenkins <charlie@...osinc.com>
> ---
> arch/riscv/Kconfig | 1 +
> arch/riscv/include/asm/cpufeature.h | 7 +
> arch/riscv/include/asm/misaligned_access_speed.h | 29 +++
> arch/riscv/kernel/Makefile | 3 +
> arch/riscv/kernel/cpufeature.c | 255 ----------------------
> arch/riscv/kernel/misaligned_access_speed.c | 265 +++++++++++++++++++++++
> arch/riscv/kernel/sys_hwprobe.c | 4 +
> 7 files changed, 309 insertions(+), 255 deletions(-)
>
> diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
> index f71910718053..8be7f17da9ab 100644
> --- a/arch/riscv/kernel/Makefile
> +++ b/arch/riscv/kernel/Makefile
> @@ -62,6 +62,9 @@ obj-y += tests/
> obj-$(CONFIG_MMU) += vdso.o vdso/
>
> obj-$(CONFIG_RISCV_MISALIGNED) += traps_misaligned.o
> +ifneq ($(RISCV_EFFICIENT_UNALIGNED_ACCESS), y)
Should this be CONFIG_RISCV_EFFICIENT_UNALIGNED_ACCESS ?
> +obj-y += misaligned_access_speed.o
> +endif
> obj-$(CONFIG_FPU) += fpu.o
> obj-$(CONFIG_RISCV_ISA_V) += vector.o
> obj-$(CONFIG_RISCV_ISA_V) += kernel_mode_vector.o
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