linux-kernel - Re: [PATCH v2] dt-bindings: media: Add sram-size Property for Wave5

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Date: Fri, 2 Feb 2024 06:52:57 -0600
From: Nishanth Menon <nm@...com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
CC: Brandon Brnich <b-brnich@...com>, Nas Chung <nas.chung@...psnmedia.com>,
        Jackson Lee <jackson.lee@...psnmedia.com>,
        Mauro Carvalho Chehab
	<mchehab@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski
	<krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley <conor+dt@...nel.org>, <linux-media@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        Vignesh Raghavendra <vigneshr@...com>,
        Darren
 Etheridge <detheridge@...com>
Subject: Re: [PATCH v2] dt-bindings: media: Add sram-size Property for Wave5

On 11:47-20240202, Krzysztof Kozlowski wrote:
> On 01/02/2024 19:42, Brandon Brnich wrote:
> > Wave521c has capability to use SRAM carveout to store reference data with
> > purpose of reducing memory bandwidth. To properly use this pool, the driver
> > expects to have an sram and sram-size node. Without sram-size node, driver
> > will default value to zero, making sram node irrelevant.
> 
> I am sorry, but what driver expects should not be rationale for new
> property. This justification suggests clearly it is not a property for DT.
> 

Yup, the argumentation in the commit message is from the wrong
perspective. bindings are OS agnostic hardware description, and what
driver does with the description is driver's problem.

I will at least paraphrase my understanding:
In this case, however, the hardware block will limp along with
the usage of DDR (as is the current description), due to the
latencies involved for DDR accesses. However, the hardware block
has capability to use a substantially lower latency SRAM to provide
proper performance and hence for example, deal with higher resolution
data streams. This SRAM is instantiated at SoC level rather than
embedded within the hardware block itself.

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D