linux-kernel - Re: [PATCH 1/3] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Update interrupts

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date: Sat, 3 Feb 2024 15:27:52 +0000
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Conor Dooley <conor@...nel.org>
Cc: Thomas Gleixner <tglx@...utronix.de>, Rob Herring <robh+dt@...nel.org>, 
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Conor Dooley <conor+dt@...nel.org>, 
	Geert Uytterhoeven <geert+renesas@...der.be>, Magnus Damm <magnus.damm@...il.com>, 
	devicetree@...r.kernel.org, linux-renesas-soc@...r.kernel.org, 
	linux-kernel@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>, 
	Claudiu Beznea <claudiu.beznea.uj@...renesas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH 1/3] dt-bindings: interrupt-controller:
 renesas,rzg2l-irqc: Update interrupts

Hi Conor,

Thank you for the review.

On Fri, Feb 2, 2024 at 5:07 PM Conor Dooley <conor@...nel.org> wrote:
>
> On Fri, Feb 02, 2024 at 09:39:05AM +0000, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >
> > RZ/{G2L, G2LC}, RZ/G2UL, RZ/V2L and RZ/G3S SoCs have ECCRAM0/1 interrupts,
> > reflect the same in the DT binding doc.
>
> Renesas' naming scheme really does not help here, but using the
> shorthands in the commit message when the diff uses the long form names
> is not the easiest thing to follow. (:
>
Sure I'll elabore the SoCs according to the binding doc so that it's more clear.
> >
> > RZ/G3S SoC has ECCRAM0/1 interrupts combined into single interrupts so
> > we just use the below to represent them:
> > - ec7tie1-0
> > - ec7tie2-0
> > - ec7tiovf-0
>
> I think this information would be good in the itemised description,
> since that claims these interrupt are only for ECCRAM0.
>
Sure 'll update as below:

+      - const: ec7tie1-0   # For RZ/G3S SoC ECCRAM0/1 interrupts combined
+      - const: ec7tie2-0   # For RZ/G3S SoC ECCRAM0/1 interrupts combined
+      - const: ec7tiovf-0  # For RZ/G3S SoC ECCRAM0/1 interrupts combined

>
> > Additionally mark 'interrupt-names' property as required for all the SoCs
> > and update the example node in the binding doc.
>
> Why? You've not given a reason for doing this, so it just seems
> gratuitous.
>
Previous assumption was just the RZ/G2UL and RZ/G3S had the bus-err
and eccram error interrupts, but where as in actual all the above SoCs
have this interrupt so making interrupt-names as required so we can
parse them based on names.

Cheers,
Prabhakar