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Date: Mon, 5 Feb 2024 22:49:23 +0530
From: Anand Moon <linux.amoon@...il.com>
To: Neil Armstrong <neil.armstrong@...aro.org>,
Kevin Hilman <khilman@...libre.com>,
Jerome Brunet <jbrunet@...libre.com>,
Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: Anand Moon <linux.amoon@...il.com>,
linux-arm-kernel@...ts.infradead.org,
linux-amlogic@...ts.infradead.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCHv1 5/5] arm64: dts: amlogic: Add cache information to the Amlogic A7 SoC
As per A311D datasheet add missing cache information to the Amlogic A7 SoC.
- Each Cortex-A53 core has 32 KB of instruction cache and
32 KB of L1 data cache available.
- Each Cortex-A73 core has 64 KB of L1 instruction cache and
64 KB of L1 data cache available.
- The little (A53) cluster has 512 KB of unified L2 cache available.
- The big (A73) cluster has 1 MB of unified L2 cache available.
To improve system performance.
Signed-off-by: Anand Moon <linux.amoon@...il.com>
---
[0] https://dl.khadas.com/products/vim4/datasheet/a311d2_quick_reference_manual_v0.6.pdf
[1] https://en.wikipedia.org/wiki/ARM_Cortex-A73
[2] https://en.wikipedia.org/wiki/ARM_Cortex-A53
---
arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 74 +++++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
index a03c7667d2b6..72dedc40f460 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
@@ -52,6 +52,13 @@ cpu100: cpu@100 {
compatible = "arm,cortex-a53";
reg = <0x0 0x100>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
+ next-level-cache = <&l2_cache_l>;
};
cpu101: cpu@...{
@@ -59,6 +66,13 @@ cpu101: cpu@...{
compatible = "arm,cortex-a53";
reg = <0x0 0x101>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
+ next-level-cache = <&l2_cache_l>;
};
cpu102: cpu@102 {
@@ -66,6 +80,13 @@ cpu102: cpu@102 {
compatible = "arm,cortex-a53";
reg = <0x0 0x102>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
+ next-level-cache = <&l2_cache_l>;
};
cpu103: cpu@103 {
@@ -73,6 +94,13 @@ cpu103: cpu@103 {
compatible = "arm,cortex-a53";
reg = <0x0 0x103>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
+ next-level-cache = <&l2_cache_l>;
};
cpu0: cpu@0 {
@@ -80,6 +108,13 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a73";
reg = <0x0 0x0>;
enable-method = "psci";
+ d-cache-line-size = <64>;
+ d-cache-size = <0x10000>;
+ d-cache-sets = <64>;
+ i-cache-line-size = <64>;
+ i-cache-size = <0x10000>;
+ i-cache-sets = <64>;
+ next-level-cache = <&l2_cache_b>;
};
cpu1: cpu@1 {
@@ -87,6 +122,13 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a73";
reg = <0x0 0x1>;
enable-method = "psci";
+ d-cache-line-size = <64>;
+ d-cache-size = <0x10000>;
+ d-cache-sets = <64>;
+ i-cache-line-size = <64>;
+ i-cache-size = <0x10000>;
+ i-cache-sets = <64>;
+ next-level-cache = <&l2_cache_b>;
};
cpu2: cpu@2 {
@@ -94,6 +136,13 @@ cpu2: cpu@2 {
compatible = "arm,cortex-a73";
reg = <0x0 0x2>;
enable-method = "psci";
+ d-cache-line-size = <64>;
+ d-cache-size = <0x10000>;
+ d-cache-sets = <64>;
+ i-cache-line-size = <64>;
+ i-cache-size = <0x10000>;
+ i-cache-sets = <64>;
+ next-level-cache = <&l2_cache_b>;
};
cpu3: cpu@3 {
@@ -101,6 +150,31 @@ cpu3: cpu@3 {
compatible = "arm,cortex-a73";
reg = <0x0 0x3>;
enable-method = "psci";
+ d-cache-line-size = <64>;
+ d-cache-size = <0x10000>;
+ d-cache-sets = <64>;
+ i-cache-line-size = <64>;
+ i-cache-size = <0x10000>;
+ i-cache-sets = <64>;
+ next-level-cache = <&l2_cache_b>;
+ };
+
+ l2_cache_l: l2-cache-cluster0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x80000>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ };
+
+ l2_cache_b: l2-cache-cluster1 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x100000>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
};
};
--
2.43.0
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