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Message-ID: <20240205184326.78814-1-sauravsc@amazon.com>
Date: Mon, 5 Feb 2024 18:43:26 +0000
From: Saurav Sachidanand <sauravsc@...zon.com>
To: Marc Zyngier <maz@...nel.org>, Oliver Upton <oliver.upton@...ux.dev>,
James Morse <james.morse@....com>, Suzuki K Poulose <suzuki.poulose@....com>,
Zenghui Yu <yuzenghui@...wei.com>, Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>
CC: Saurav Sachidanand <sauravsc@...zon.com>,
<linux-arm-kernel@...ts.infradead.org>, <kvmarm@...ts.linux.dev>,
<linux-kernel@...r.kernel.org>
Subject: [PATCH] [RFC] KVM: arm64/vgic: Populate GICR_TYPER with Aff3
According to spec, bits [63:56] of the GICR_TYPER register are supposed
to contain Affinity level 3 (Aff3) bits of the Processing Element (PE)
associated with its GIC redistributor. Linux guests on boot match PEs
with their redistributor using all four Affinity level bits from this
register.
Currently, vGIC populates GICR_TYPER with just the first three Affinity
levels of a vCPU's MPIDR. This works fine for a Linux guest that boots
with KVM's default vCPU MPIDR assignment, which also only populates till
the first three Affinity levels.
However, a hypervisor can override KVM's default MPIDR assignment by
writing directly to a vCPU's MPIDR_EL1 register. If such a hypervisor
were to populate Aff3 bits for a VM, a Linux guest booting there would
fail to match vCPUs with their vGIC redistributors, since their virtual
GICR_TYPER registers would be missing the respective Aff3 bits.
To change that, let's populate GICR_TYPER using Aff3 bits [39:32] from
the vCPU's MPIDR.
Signed-off-by: Saurav Sachidanand <sauravsc@...zon.com>
---
arch/arm64/kvm/vgic/vgic-mmio-v3.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/kvm/vgic/vgic-mmio-v3.c b/arch/arm64/kvm/vgic/vgic-mmio-v3.c
index c15ee1df036a..26bc838ce14c 100644
--- a/arch/arm64/kvm/vgic/vgic-mmio-v3.c
+++ b/arch/arm64/kvm/vgic/vgic-mmio-v3.c
@@ -324,6 +324,7 @@ static unsigned long vgic_mmio_read_v3r_typer(struct kvm_vcpu *vcpu,
u64 value;
value = (u64)(mpidr & GENMASK(23, 0)) << 32;
+ value |= (u64)((mpidr >> 32) & GENMASK(7, 0)) << 56;
value |= ((target_vcpu_id & 0xffff) << 8);
if (vgic_has_its(vcpu->kvm))
--
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