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Message-ID: <20240206143711.2410135-1-msp@baylibre.com>
Date: Tue, 6 Feb 2024 15:37:07 +0100
From: Markus Schneider-Pargmann <msp@...libre.com>
To: Nishanth Menon <nm@...com>,
Vignesh Raghavendra <vigneshr@...com>,
Tero Kristo <kristo@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Srinivas Kandagatla <srinivas.kandagatla@...aro.org>,
Santosh Shilimkar <ssantosh@...nel.org>
Cc: Andrew Davis <afd@...com>,
linux-arm-kernel@...ts.infradead.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Markus Schneider-Pargmann <msp@...libre.com>
Subject: [PATCH 0/4] soc: ti: k3-socinfo: Add support for nvmem cells
Hi,
am62 has a number of efuse fields that are situated in the device range
of the current chipid device node. As other devices require these
information as well, I am trying to establish a new nvmem layout for the
information available in this register range.
In this series the conflicting chipid driver is updated to support
nvmem-cells and the chipid node gets the register range removed and
replaced with nvmem cells on am62.
In a follow-up series the opp table will be updated.
Best,
Markus
Markus Schneider-Pargmann (4):
nvmem: core: Read into buffers larger than data
dt-bindings: hwinfo: ti,k3-socinfo: Add nvmem-cells
soc: ti: k3-socinfo: Add support for nvmem cells
arm64: dts: ti: k3-am62-wakeup: Add chip efuse nodes
.../bindings/hwinfo/ti,k3-socinfo.yaml | 23 ++++++-
arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 36 +++++++++-
drivers/nvmem/core.c | 6 +-
drivers/soc/ti/k3-socinfo.c | 67 +++++++++++++------
4 files changed, 107 insertions(+), 25 deletions(-)
--
2.43.0
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