linux-kernel - Re: [PATCH 2/2] arm64: dts: imx8dxl update edma0 information

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Message-ID: <ZcJPOldJBIo3E7RK@lizhi-Precision-Tower-5810>
Date: Tue, 6 Feb 2024 10:24:42 -0500
From: Frank Li <Frank.li@....com>
To: Shawn Guo <shawnguo2@...h.net>
Cc: Rob Herring <robh+dt@...nel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
	Conor Dooley <conor+dt@...nel.org>, Shawn Guo <shawnguo@...nel.org>,
	Sascha Hauer <s.hauer@...gutronix.de>,
	Pengutronix Kernel Team <kernel@...gutronix.de>,
	Fabio Estevam <festevam@...il.com>,
	NXP Linux Team <linux-imx@....com>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@...r.kernel.org>,
	"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" <linux-arm-kernel@...ts.infradead.org>,
	open list <linux-kernel@...r.kernel.org>, imx@...ts.linux.dev
Subject: Re: [PATCH 2/2] arm64: dts: imx8dxl update edma0 information

On Tue, Feb 06, 2024 at 06:38:29PM +0800, Shawn Guo wrote:
> On Mon, Jan 29, 2024 at 03:16:32PM -0500, Frank Li wrote:
> > edma0 of iMX8DXL is difference with other imx8 chips. Update register's
> > size, channel number and power-domain.
> > Update i2c[0-3] channel number information.
> > 
> > Signed-off-by: Frank Li <Frank.Li@....com>
> > ---
> >  .../boot/dts/freescale/imx8dxl-ss-adma.dtsi   | 65 +++++++++++++++++++
> >  1 file changed, 65 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
> > index 0a477f6318f15..f8fca86babda7 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
> > @@ -15,6 +15,63 @@ &adc0 {
> >  	interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
> >  };
> >  
> > +&edma0 {
> > +	reg = <0x591f0000 0x1a0000>;
> > +	#dma-cells = <3>;
> > +	dma-channels = <25>;
> > +	dma-channel-mask = <0x1c0cc0>;
> > +	interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, /* asrc 0 */
> > +		<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
> > +		<GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
> > +		<GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
> > +		<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
> > +		<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
> > +		<GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH>,
> > +		<GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH>,
> > +		<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */
> > +		<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
> > +		<GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH>,
> > +		<GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH>,
> > +		<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */
> > +		<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
> > +		<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */
> > +		<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
> > +		<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* sai2 */
> > +		<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* sai3 */
> > +		<GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH>,
> > +		<GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH>,
> > +		<GIC_SPI 0   IRQ_TYPE_LEVEL_HIGH>,
> > +		<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* gpt0 */
> > +		<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, /* gpt1 */
> > +		<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, /* gpt2 */
> > +		<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>; /* gpt3 */
> > +	power-domains = <&pd IMX_SC_R_DMA_0_CH0>,
> > +			<&pd IMX_SC_R_DMA_0_CH1>,
> > +			<&pd IMX_SC_R_DMA_0_CH2>,
> > +			<&pd IMX_SC_R_DMA_0_CH3>,
> > +			<&pd IMX_SC_R_DMA_0_CH4>,
> > +			<&pd IMX_SC_R_DMA_0_CH5>,
> > +			<&pd IMX_SC_R_DMA_0_CH6>,
> > +			<&pd IMX_SC_R_DMA_0_CH7>,
> > +			<&pd IMX_SC_R_DMA_0_CH8>,
> > +			<&pd IMX_SC_R_DMA_0_CH9>,
> > +			<&pd IMX_SC_R_DMA_0_CH10>,
> > +			<&pd IMX_SC_R_DMA_0_CH11>,
> > +			<&pd IMX_SC_R_DMA_0_CH12>,
> > +			<&pd IMX_SC_R_DMA_0_CH13>,
> > +			<&pd IMX_SC_R_DMA_0_CH14>,
> > +			<&pd IMX_SC_R_DMA_0_CH15>,
> > +			<&pd IMX_SC_R_DMA_0_CH16>,
> > +			<&pd IMX_SC_R_DMA_0_CH17>,
> > +			<&pd IMX_SC_R_DMA_0_CH18>,
> > +			<&pd IMX_SC_R_DMA_0_CH19>,
> > +			<&pd IMX_SC_R_DMA_0_CH20>,
> > +			<&pd IMX_SC_R_DMA_0_CH21>,
> > +			<&pd IMX_SC_R_DMA_0_CH22>,
> > +			<&pd IMX_SC_R_DMA_0_CH23>,
> > +			<&pd IMX_SC_R_DMA_0_CH24>;
> > +};
> > +
> >  &edma2 {
> >  	interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
> >  		     <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
> > @@ -48,21 +105,29 @@ &edma3 {
> >  &i2c0 {
> >  	compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c";
> >  	interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
> > +	dma-names = "tx","rx";
> > +	dmas = <&edma3 1 0 0>, <&edma3 0 0 FSL_EDMA_RX>;
> >  };
> >  
> >  &i2c1 {
> >  	compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c";
> >  	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
> > +	dma-names = "tx","rx";
> > +	dmas = <&edma3 3 0 0>, <&edma3 2 0 FSL_EDMA_RX>;
> 
> No FSL_EDMA_TX for "tx"?

Yes, only defined FSL_EDMA_RX. It is bitmask. If no FSL_EDMA_RX, means
TX channel.

Frank

> 
> Shawn
> 
> >  };
> >  
> >  &i2c2 {
> >  	compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c";
> >  	interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
> > +	dma-names = "tx","rx";
> > +	dmas = <&edma3 5 0 0>, <&edma3 4 0 FSL_EDMA_RX>;
> >  };
> >  
> >  &i2c3 {
> >  	compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c";
> >  	interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
> > +	dma-names = "tx","rx";
> > +	dmas = <&edma3 7 0 0>, <&edma3 6 0 FSL_EDMA_RX>;
> >  };
> >  
> >  &lpuart0 {
> > -- 
> > 2.34.1
> > 
>