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Message-ID: <ea0820be-391d-4b40-be89-df91524780dd@linaro.org>
Date: Tue, 6 Feb 2024 17:51:42 +0100
From: Konrad Dybcio <konrad.dybcio@...aro.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
Bjorn Andersson <andersson@...nel.org>, Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] arm64: dts: qcom: sc8180x: describe all PCI MSI
interrupts
On 5.02.2024 17:31, Krzysztof Kozlowski wrote:
> Each group of MSI interrupts is mapped to the separate host interrupt.
> Describe each of interrupts in the device tree for PCIe hosts. This
> also corrects PCIe1 and PCIe2 first MSI interrupt.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
>
> ---
>
> Not tested on HW.
Booted sc8180x-primus, NVMe is still accessible
Tested-by: Konrad Dybcio <konrad.dybcio@...aro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@...aro.org>
Konrad
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