linux-kernel - [PATCH v2 1/5] dt-bindings: arm: msm: Add llcc Broadcast

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Message-ID: <53ba029fb1e3f66505b9f6487030e5d981e1621f.1707202761.git.quic_uchalich@quicinc.com>
Date: Mon, 5 Feb 2024 23:15:52 -0800
From: Unnathi Chalicheemala <quic_uchalich@...cinc.com>
To: Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio
	<konrad.dybcio@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        "Krzysztof
 Kozlowski" <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley
	<conor+dt@...nel.org>
CC: <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <kernel@...cinc.com>,
        Krzysztof Kozlowski
	<krzysztof.kozlowski@...aro.org>
Subject: [PATCH v2 1/5] dt-bindings: arm: msm: Add llcc Broadcast_AND register region

The LLCC driver in SM8450, SM8550 and SM8650 have a new register
space for Broadcast_AND region. This is used to check that all
channels have bit set to "1", mainly in SCID activation/deactivation.

Previously we were mapping only the Broadcast_OR region assuming
there was only one broadcast register region. Now we also map
Broadcast_AND region.

Signed-off-by: Unnathi Chalicheemala <quic_uchalich@...cinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
---
 .../devicetree/bindings/cache/qcom,llcc.yaml  | 41 +++++++++++++++----
 1 file changed, 33 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
index 07ccbda4a0ab..b12ac4308284 100644
--- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
+++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
@@ -141,8 +141,31 @@ allOf:
               - qcom,sm8150-llcc
               - qcom,sm8250-llcc
               - qcom,sm8350-llcc
+    then:
+      properties:
+        reg:
+          items:
+            - description: LLCC0 base register region
+            - description: LLCC1 base register region
+            - description: LLCC2 base register region
+            - description: LLCC3 base register region
+            - description: LLCC broadcast base register region
+        reg-names:
+          items:
+            - const: llcc0_base
+            - const: llcc1_base
+            - const: llcc2_base
+            - const: llcc3_base
+            - const: llcc_broadcast_base
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
               - qcom,sm8450-llcc
               - qcom,sm8550-llcc
+              - qcom,sm8650-llcc
     then:
       properties:
         reg:
@@ -151,7 +174,8 @@ allOf:
             - description: LLCC1 base register region
             - description: LLCC2 base register region
             - description: LLCC3 base register region
-            - description: LLCC broadcast base register region
+            - description: LLCC broadcast OR register region
+            - description: LLCC broadcast AND register region
         reg-names:
           items:
             - const: llcc0_base
@@ -159,6 +183,7 @@ allOf:
             - const: llcc2_base
             - const: llcc3_base
             - const: llcc_broadcast_base
+            - const: llcc_broadcast_and_base
 
 additionalProperties: false
 
@@ -170,13 +195,13 @@ examples:
         #address-cells = <2>;
         #size-cells = <2>;
 
-        system-cache-controller@...0000 {
-            compatible = "qcom,sdm845-llcc";
-            reg = <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>,
-                <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>,
-                <0 0x01300000 0 0x50000>;
+        system-cache-controller@...00000 {
+            compatible = "qcom,sm8550-llcc";
+            reg = <0 0x25200000 0 0x200000>, <0 0x25400000 0 0x200000>,
+                <0 0x25600000 0 0x200000>, <0 0x25800000 0 0x200000>,
+                <0 0x25a00000 0 0x200000>;
             reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
-                "llcc3_base", "llcc_broadcast_base";
-            interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
+                "llcc3_base", "llcc_broadcast_base", "llcc_broadcast_and_base";
+            interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
         };
     };
-- 
2.25.1