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Date: Tue, 6 Feb 2024 10:43:58 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Krishna Kurapati PSSNV <quic_kriskura@...cinc.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Rob Herring <robh+dt@...nel.org>, 
	Bjorn Andersson <andersson@...nel.org>, Wesley Cheng <quic_wcheng@...cinc.com>, 
	Konrad Dybcio <konrad.dybcio@...aro.org>, Greg Kroah-Hartman <gregkh@...uxfoundation.org>, 
	Conor Dooley <conor+dt@...nel.org>, Thinh Nguyen <Thinh.Nguyen@...opsys.com>, 
	Felipe Balbi <balbi@...nel.org>, devicetree@...r.kernel.org, 
	linux-arm-msm@...r.kernel.org, linux-usb@...r.kernel.org, 
	linux-kernel@...r.kernel.org, quic_ppratap@...cinc.com, 
	quic_jackp@...cinc.com
Subject: Re: [PATCH v14 0/9] Add multiport support for DWC3 controllers

On Tue, 6 Feb 2024 at 10:15, Krishna Kurapati PSSNV
<quic_kriskura@...cinc.com> wrote:
>
>
>
> On 2/6/2024 1:30 PM, Dmitry Baryshkov wrote:
> > Hi Krishna,
> >
> > On Tue, 6 Feb 2024 at 07:18, Krishna Kurapati <quic_kriskura@...cinc.com> wrote:
> >>
> >> Currently the DWC3 driver supports only single port controller which
> >> requires at most two PHYs ie HS and SS PHYs. There are SoCs that has
> >> DWC3 controller with multiple ports that can operate in host mode.
> >> Some of the port supports both SS+HS and other port supports only HS
> >> mode.
> >>
> >> This change primarily refactors the Phy logic in core driver to allow
> >> multiport support with Generic Phy's.
> >>
> >> Changes have been tested on  QCOM SoC SA8295P which has 4 ports (2
> >> are HS+SS capable and 2 are HS only capable).
> >
> > Thank you for your patches! Have you tested how this patchset
> > interacts with the USB role-switching?
> >
> > I'm asking because it might be easier to define DT nodes for each of
> > USB ports, which can carry the PHY properties (and also other DT
> > properties if that's required, e.g. the ports / endpoints and
> > usb-role-switch) rather than pushing all USB PHY links to the root DT
> > node.
> >
>
> Hi Dmitry,
>
>   Role switching doesn't work for Multiport controller as it is host
> only capable. I don't think it will cause any issues for OTG capable
> controllers because they only have one HS and SS phy present. So there
> is no possibility or requirement for having endpoints per port in this case.

Is it going to remain host-only in future?



--
With best wishes
Dmitry

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