linux-kernel - Re: [PATCH 2/4] arm64: dts: exynos: gs101: add chipid node

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Message-ID: <b199ba24-403b-44fa-b807-9b98f9e98913@linaro.org>
Date: Tue, 6 Feb 2024 11:10:07 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Peter Griffin <peter.griffin@...aro.org>,
 Alexey Klimov <alexey.klimov@...aro.org>
Cc: alim.akhtar@...sung.com, linux-samsung-soc@...r.kernel.org,
 semen.protsenko@...aro.org, robh+dt@...nel.org,
 krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
 devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 linux-kernel@...r.kernel.org, klimov.linux@...il.com,
 kernel-team@...roid.com, tudor.ambarus@...aro.org, andre.draszik@...aro.org,
 saravanak@...gle.com, willmcvicker@...gle.com, arnd@...db.de
Subject: Re: [PATCH 2/4] arm64: dts: exynos: gs101: add chipid node

On 05/02/2024 15:36, Peter Griffin wrote:
> Hi Alexey & Krysztof,
> 
> On Thu, 1 Feb 2024 at 17:22, Alexey Klimov <alexey.klimov@...aro.org> wrote:
>>
>> Signed-off-by: Alexey Klimov <alexey.klimov@...aro.org>
>> ---
>>  arch/arm64/boot/dts/exynos/google/gs101.dtsi | 5 +++++
>>  1 file changed, 5 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
>> index d838e3a7af6e..156fec2575bc 100644
>> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
>> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
>> @@ -283,6 +283,11 @@ soc: soc@0 {
>>                 #size-cells = <1>;
>>                 ranges = <0x0 0x0 0x0 0x40000000>;
>>
>> +               chipid@...00000 {
>> +                       compatible = "google,gs101-chipid";
>> +                       reg = <0x10000000 0xd000>;
>> +               };
>> +
> 
> I was wondering about the 0xd000 size here, as most upstream platforms
> use a chipid size of 0x100 or 0x24. I see the downstream gs101 kernel
> also uses 0xd000. Looking a bit more, that is because gs-chipid.c also
> has support for dumping other areas of the OTP SFR bank like asv table
> (offset 0x9000) hpm_asv (offset 0xa000) and hw_tune (0xc000).
> 
> I checked Exynos850 and that also has ASV tables at those same offsets
> above, but it currently uses a chipid size of 0x100 upstream.
> Exynos-asv.c driver is part of exynos-chipid.c upstream so it seems
> reasonable to have the increased size including those SFR registers.
> Currently exynos-asv.c driver only supports Exynos5422 upstream.
> 
> @Krzysztof - From a process PoV what is the best/correct thing to do
> here? Have the increased size in DT that includes ASV parts of the OTP
> bank from the get-go?

ChipID so far had only size of 0x30 or something like that. What you
refer to does not look like old ChipID but full blown OTP, which also
includes ChipID. Although I am not entirely sure about that, either.
Depends whether they share clocks, for example.

I don't have any GS101 information so I don't know what's there. It
seems you ask me to give you decision based on guessing... If you have
one block, so if there is OTP, which contains ChipID, then define OTP.
Not ChipID+OTP.

I think Exynos850 DTSI is wrong here. That's OTP block, not ChipID.

Best regards,
Krzysztof