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Message-ID: <20240207111402.576152-3-jhp@endlessos.org>
Date: Wed,  7 Feb 2024 19:14:04 +0800
From: Jian-Hong Pan <jhp@...lessos.org>
To: Bjorn Helgaas <helgaas@...nel.org>,
	Johan Hovold <johan@...nel.org>,
	Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>,
	David Box <david.e.box@...ux.intel.com>
Cc: Mika Westerberg <mika.westerberg@...ux.intel.com>,
	Nirmal Patel <nirmal.patel@...ux.intel.com>,
	Jonathan Derrick <jonathan.derrick@...ux.dev>,
	linux-pci@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	linux@...lessos.org,
	Jian-Hong Pan <jhp@...lessos.org>
Subject: [PATCH v3 2/3] PCI/ASPM: Add notes about enabling PCI-PM L1SS to pci_enable_link_state(_locked)

According to PCI Express Base Specification Revision 6.0, Section 5.5.4:
"If setting either or both of the enable bits for PCI-PM L1 PM Substates,
both ports must be configured as described in this section while in D0."

Add notes into pci_enable_link_state(_locked) for kernel-doc. Hope these
notify callers ensuring the devices in D0, if PCI-PM L1 PM Substates are
going to be enabled.

Signed-off-by: Jian-Hong Pan <jhp@...lessos.org>
---
v3:
- Fix as readable comments

 drivers/pci/pcie/aspm.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index 7f1d674ff171..a39d2ee744cb 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -1416,6 +1416,9 @@ static int __pci_enable_link_state(struct pci_dev *pdev, int state, bool locked)
  * touch the LNKCTL register. Also note that this does not enable states
  * disabled by pci_disable_link_state(). Return 0 or a negative errno.
  *
+ * Note: Ensure devices are in D0 before enabling PCI-PM L1 PM Substates, per
+ * PCIe r6.0, sec 5.5.4.
+ *
  * @pdev: PCI device
  * @state: Mask of ASPM link states to enable
  */
@@ -1432,6 +1435,9 @@ EXPORT_SYMBOL(pci_enable_link_state);
  * can't touch the LNKCTL register. Also note that this does not enable states
  * disabled by pci_disable_link_state(). Return 0 or a negative errno.
  *
+ * Note: Ensure devices are in D0 before enabling PCI-PM L1 PM Substates, per
+ * PCIe r6.0, sec 5.5.4.
+ *
  * @pdev: PCI device
  * @state: Mask of ASPM link states to enable
  *
-- 
2.43.0


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