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Message-ID: <ZcOCrearsKaZiBt/@tpad>
Date: Wed, 7 Feb 2024 10:16:29 -0300
From: Marcelo Tosatti <mtosatti@...hat.com>
To: Thomas Gleixner <tglx@...utronix.de>
Cc: linux-kernel@...r.kernel.org,
Daniel Bristot de Oliveira <bristot@...nel.org>,
Juri Lelli <juri.lelli@...hat.com>,
Valentin Schneider <vschneid@...hat.com>,
Frederic Weisbecker <frederic@...nel.org>,
Leonardo Bras <leobras@...hat.com>,
Peter Zijlstra <peterz@...radead.org>
Subject: Re: [patch 12/12] x86/cacheinfo.c: check for block interference CPUs
On Wed, Feb 07, 2024 at 10:10:41AM -0300, Marcelo Tosatti wrote:
> On Wed, Feb 07, 2024 at 01:41:36PM +0100, Thomas Gleixner wrote:
> > On Tue, Feb 06 2024 at 15:49, Marcelo Tosatti wrote:
> > > @@ -396,6 +397,7 @@ static void amd_l3_disable_index(struct
> > > * disable index in all 4 subcaches
> > > */
> > > for (i = 0; i < 4; i++) {
> > > + int ret;
> > > u32 reg = idx | (i << 20);
> > >
> > > if (!nb->l3_cache.subcaches[i])
> > > @@ -409,6 +411,7 @@ static void amd_l3_disable_index(struct
> > > * is not sufficient.
> > > */
> > > ret = wbinvd_on_cpu(cpu);
> > > + WARN_ON(ret == -EPERM);
> >
> > What? You create inconsistent state here.
>
> That should not happen, since we checked for
>
> + idx = block_interf_srcu_read_lock();
> +
> + if (block_interf_cpu(cpu))
> + ret = -EPERM;
>
> Earlier.
>
> Thus the WARN_ON (hum, can change to BUG_ON...).
>
> > > - amd_l3_disable_index(nb, cpu, slot, index);
> > > + ret = 0;
> > > + idx = block_interf_srcu_read_lock();
> > > +
> > > + if (block_interf_cpu(cpu))
> > > + ret = -EPERM;
> > > + else
> > > + amd_l3_disable_index(nb, cpu, slot, index);
> > > +
> > > + block_interf_srcu_read_unlock(idx);
> >
> > Again. This is a root only operation.
> >
> > This whole patch series is just voodoo programming with zero
> > justification for the mess it creates.
BTW, this converted less than 17% callers, so this is why early
feedback is useful.
Thanks!
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