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Date: Wed, 7 Feb 2024 21:28:02 +0530
From: Anup Patel <anup@...infault.org>
To: Ley Foon Tan <leyfoon.tan@...rfivetech.com>
Cc: Daniel Lezcano <daniel.lezcano@...aro.org>, Thomas Gleixner <tglx@...utronix.de>, 
	Palmer Dabbelt <palmer@...belt.com>, Paul Walmsley <paul.walmsley@...ive.com>, 
	Albert Ou <aou@...s.berkeley.edu>, atishp@...osinc.com, 
	linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org, 
	Ley Foon Tan <lftan.linux@...il.com>, stable@...r.kernel.org
Subject: Re: [PATCH v2] clocksource: timer-riscv: Clear timer interrupt on
 timer initialization

On Mon, Jan 29, 2024 at 1:12 PM Ley Foon Tan
<leyfoon.tan@...rfivetech.com> wrote:
>
> In the RISC-V specification, the stimecmp register doesn't have a default
> value. To prevent the timer interrupt from being triggered during timer
> initialization, clear the timer interrupt by writing stimecmp with a
> maximum value.
>
> Fixes: 9f7a8ff6391f ("RISC-V: Prefer sstc extension if available")
> Cc:  <stable@...r.kernel.org>
> Signed-off-by: Ley Foon Tan <leyfoon.tan@...rfivetech.com>

LGTM.

Reviewed-by: Anup Patel <anup@...infault.org>

Regards,
Anup

>
> ---
> v2:
> Resolved comments from Anup.
> - Moved riscv_clock_event_stop() to riscv_timer_starting_cpu().
> - Added Fixes tag
> ---
>  drivers/clocksource/timer-riscv.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> index e66dcbd66566..672669eb7281 100644
> --- a/drivers/clocksource/timer-riscv.c
> +++ b/drivers/clocksource/timer-riscv.c
> @@ -116,6 +116,9 @@ static int riscv_timer_starting_cpu(unsigned int cpu)
>                 ce->rating = 450;
>         clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff);
>
> +       /* Clear timer interrupt */
> +       riscv_clock_event_stop();
> +
>         enable_percpu_irq(riscv_clock_event_irq,
>                           irq_get_trigger_type(riscv_clock_event_irq));
>         return 0;
> --
> 2.43.0
>
>

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