lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date: Thu, 8 Feb 2024 16:14:58 +0000
From: POPESCU Catalin <catalin.popescu@...ca-geosystems.com>
To: Andrew Lunn <andrew@...n.ch>
CC: "davem@...emloft.net" <davem@...emloft.net>, "kuba@...nel.org"
	<kuba@...nel.org>, "pabeni@...hat.com" <pabeni@...hat.com>,
	"robh+dt@...nel.org" <robh+dt@...nel.org>,
	"krzysztof.kozlowski+dt@...aro.org" <krzysztof.kozlowski+dt@...aro.org>,
	"conor+dt@...nel.org" <conor+dt@...nel.org>, "afd@...com" <afd@...com>,
	"hkallweit1@...il.com" <hkallweit1@...il.com>, "linux@...linux.org.uk"
	<linux@...linux.org.uk>, "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	GEO-CHHER-bsp-development <bsp-development.geo@...ca-geosystems.com>,
	"m.felsch@...gutronix.de" <m.felsch@...gutronix.de>
Subject: Re: [PATCH v2 2/2] net: phy: dp83826: support TX data voltage tuning

Since my previous message has been rejected due to HTML content, I'm 
resending it. Sorry, for the inconvenience.

On 08.02.24 14:56, Andrew Lunn wrote:
> [Some people who received this message don't often get email from andrew@...n.ch. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> This email is not from Hexagon’s Office 365 instance. Please be careful while clicking links, opening attachments, or replying to this email.
>
>
>>> I could be reading this wrong, but it looks like
>>> DP83826_CFG_DAC_MINUS_DEFAULT actually means leave the value
>>> unchanged? Is there anything guaranteeing it does in fact have the
>>> default value in the hardware?
>>>
>>>           Andrew
>> Yes, the datasheet clearly states the default/reset values of both
>> registers VOD_CFG1 & VOD_CFG2 which are :
>> - cfg_dac_minus : 30h
>> - cfg_dac_plus : 10h
> And the device is actually and always reset by Linux when the driver
> loads? Anything the bootloader has done, or a previous kernel, will be
> cleared?
Now, I understand your question 🙂
To answer, DP83826_CFG_DAC_MINUS_DEFAULT will indeed leave the register 
unchanged. However, dp83822 driver exports a PHY callback soft_reset 
which does a SW reset which actually has the same effect as the HW reset 
pin according to the datasheet. Since the PAL enforces the call to 
soft_reset before config_init, in dp83826_config_init we can rely on the 
registers reset value.
> Please add this explanation to the commit message.
>
> I'm being pedantic because we have had problems like this in the past.
> If a register was not actually set back to the default value, the
> bootloader set it to some other value, the board can work fine. Then a
> board can came along which the bootloader set the wrong value, and the
> default is actually needed. Fixing the driver to actually enforce the
> default breaks boards...
>
>           Andrew


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ