linux-kernel - Re: [PATCH 2/2] platform/chrome: cros_ec_typec: Make sure the USB role switch has PLD

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <CACeCKaffZBPA0Q_Bqs1hjKJB4HCj=VKrqO21dXj4AF5C5VwtVQ@mail.gmail.com>
Date: Thu, 8 Feb 2024 10:14:21 -0800
From: Prashant Malani <pmalani@...omium.org>
To: Heikki Krogerus <heikki.krogerus@...ux.intel.com>
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>, Benson Leung <bleung@...omium.org>, 
	Tzung-Bi Shih <tzungbi@...nel.org>, Guenter Roeck <groeck@...omium.org>, 
	Emilie Roberts <hadrosaur@...gle.com>, "Nyman, Mathias" <mathias.nyman@...el.com>, 
	"Regupathy, Rajaram" <rajaram.regupathy@...el.com>, 
	"Radjacoumar, Shyam Sundar" <ssradjacoumar@...gle.com>, Samuel Jacob <samjaco@...gle.com>, linux-usb@...r.kernel.org, 
	chrome-platform@...ts.linux.dev, linux-kernel@...r.kernel.org, 
	Uday Bhat <uday.m.bhat@...el.com>
Subject: Re: [PATCH 2/2] platform/chrome: cros_ec_typec: Make sure the USB
 role switch has PLD

Hi Heikki,

On Wed, Feb 7, 2024 at 6:59 AM Heikki Krogerus
<heikki.krogerus@...ux.intel.com> wrote:
>
> The USB role switch does not always have the _PLD (Physical
> Location of Device) in ACPI tables. If it's missing,
> assigning the PLD hash of the port to the switch. That
> should guarantee that the USB Type-C port mapping code is
> always able to find the connection between the two (the port
> and the switch).
>
> Tested-by: Uday Bhat <uday.m.bhat@...el.com>
> Signed-off-by: Heikki Krogerus <heikki.krogerus@...ux.intel.com>
> ---
>  drivers/platform/chrome/cros_ec_typec.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
>
> diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chrome/cros_ec_typec.c
> index 2b2f14a1b711..5c14e8db08b5 100644
> --- a/drivers/platform/chrome/cros_ec_typec.c
> +++ b/drivers/platform/chrome/cros_ec_typec.c
> @@ -28,6 +28,7 @@ static int cros_typec_parse_port_props(struct typec_capability *cap,
>                                        struct fwnode_handle *fwnode,
>                                        struct device *dev)
>  {
> +       struct fwnode_handle *sw_fwnode;
>         const char *buf;
>         int ret;
>
> @@ -66,6 +67,16 @@ static int cros_typec_parse_port_props(struct typec_capability *cap,
>                 cap->prefer_role = ret;
>         }
>
> +       /* Assing the USB role switch the correct pld_crc if it's missing */
> +       sw_fwnode = fwnode_find_reference(fwnode, "usb-role-switch", 0);
> +       if (!IS_ERR_OR_NULL(sw_fwnode)) {
> +               struct acpi_device *adev = to_acpi_device_node(sw_fwnode);
> +
> +               if (adev && !adev->pld_crc)
> +                       adev->pld_crc = to_acpi_device_node(fwnode)->pld_crc;
> +               fwnode_handle_put(sw_fwnode);
Can this be in common Type-C code (maybe typec_register_port())?
It doesn't strike me as ChromeOS specific, but perhaps I am missing something.

Thanks,