linux-kernel - Re: [PATCH] arm64: dts: qcom: qcs6490-rb3gen2: Add PCIe nodes

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Date: Thu, 8 Feb 2024 11:44:02 +0530
From: Krishna Chaitanya Chundru <quic_krichai@...cinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
CC: Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio
	<konrad.dybcio@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        "Krzysztof
 Kozlowski" <krzysztof.kozlowski+dt@...aro.org>,
        Conor Dooley
	<conor+dt@...nel.org>, <linux-arm-msm@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <quic_vbadigan@...cinc.com>, <quic_ramkri@...cinc.com>,
        <quic_nitegupt@...cinc.com>, <quic_skananth@...cinc.com>,
        <quic_parass@...cinc.com>
Subject: Re: [PATCH] arm64: dts: qcom: qcs6490-rb3gen2: Add PCIe nodes



On 2/7/2024 5:17 PM, Dmitry Baryshkov wrote:
> On Wed, 7 Feb 2024 at 12:42, Krishna chaitanya chundru
> <quic_krichai@...cinc.com> wrote:
>>
>> Enable PCIe1 controller and its corresponding PHY nodes on
>> qcs6490-rb3g2 platform.
>>
>> PCIe switch is connected to PCIe1, PCIe switch has multiple endpoints
>> connected. For each endpoint a unique BDF will be assigned and should
>> assign unique smmu id. So for each BDF add smmu id.
>>
>> Signed-off-by: Krishna chaitanya chundru <quic_krichai@...cinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 42 ++++++++++++++++++++++++++++
>>   1 file changed, 42 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
>> index 8bb7d13d85f6..0082a3399453 100644
>> --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
>> +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
>> @@ -413,6 +413,32 @@ vreg_bob_3p296: bob {
>>          };
>>   };
>>
>> +&pcie1 {
>> +       perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
>> +
>> +       pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>;
>> +       pinctrl-names = "default";
>> +
>> +       iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
>> +                   <0x100 &apps_smmu 0x1c81 0x1>,
>> +                   <0x208 &apps_smmu 0x1c84 0x1>,
>> +                   <0x210 &apps_smmu 0x1c85 0x1>,
>> +                   <0x218 &apps_smmu 0x1c86 0x1>,
>> +                   <0x300 &apps_smmu 0x1c87 0x1>,
>> +                   <0x400 &apps_smmu 0x1c88 0x1>,
>> +                   <0x500 &apps_smmu 0x1c89 0x1>,
>> +                   <0x501 &apps_smmu 0x1c90 0x1>;
> 
> Is the iommu-map really board specific?
> 
The iommu-map for PCIe varies if PCIe switch is connected.
For this platform a PCIe switch is connected and for that reason
we need to define additional smmu ID's for each BDF.

For that reason we defined here as these ID's are applicable only
for this board.

- Krishna Chaitanya.
>> +
>> +       status = "okay";
>> +};
>> +
>> +&pcie1_phy {
>> +       vdda-phy-supply = <&vreg_l10c_0p88>;
>> +       vdda-pll-supply = <&vreg_l6b_1p2>;
>> +
>> +       status = "okay";
>> +};
>> +
>>   &qupv3_id_0 {
>>          status = "okay";
>>   };
>> @@ -420,6 +446,22 @@ &qupv3_id_0 {
>>   &tlmm {
>>          gpio-reserved-ranges = <32 2>, /* ADSP */
>>                                 <48 4>; /* NFC */
>> +
>> +       pcie1_reset_n: pcie1-reset-n-state {
>> +               pins = "gpio2";
>> +               function = "gpio";
>> +               drive-strength = <16>;
>> +               output-low;
>> +               bias-disable;
>> +       };
>> +
>> +       pcie1_wake_n: pcie1-wake-n-state {
>> +               pins = "gpio3";
>> +               function = "gpio";
>> +               drive-strength = <2>;
>> +               bias-pull-up;
>> +       };
>> +
>>   };
>>
>>   &uart5 {
>>
>> ---
>> base-commit: 70d201a40823acba23899342d62bc2644051ad2e
>> change-id: 20240207-enable_pcie-95b1d6612b27
>>
>> Best regards,
>> --
>> Krishna chaitanya chundru <quic_krichai@...cinc.com>
>>
>>
> 
>