linux-kernel - Re: [RFC PATCH 0/5] RISC-V: Add dynamic TSO support

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Message-ID: <ZcS2vDZjQzDARefn@andrea>
Date: Thu, 8 Feb 2024 12:10:52 +0100
From: Andrea Parri <parri.andrea@...il.com>
To: Jonas Oberhauser <jonas.oberhauser@...weicloud.com>
Cc: Peter Zijlstra <peterz@...radead.org>,
	Christoph Muellner <christoph.muellner@...ll.eu>,
	linux-riscv@...ts.infradead.org, linux-kselftest@...r.kernel.org,
	linux-kernel@...r.kernel.org, linux-doc@...r.kernel.org,
	Palmer Dabbelt <palmer@...belt.com>,
	Paul Walmsley <paul.walmsley@...ive.com>,
	Albert Ou <aou@...s.berkeley.edu>,
	Andrew Morton <akpm@...ux-foundation.org>,
	Shuah Khan <shuah@...nel.org>, Jonathan Corbet <corbet@....net>,
	Anup Patel <apatel@...tanamicro.com>,
	Philipp Tomsich <philipp.tomsich@...ll.eu>,
	Andrew Jones <ajones@...tanamicro.com>, Guo Ren <guoren@...nel.org>,
	Daniel Henrique Barboza <dbarboza@...tanamicro.com>,
	Conor Dooley <conor.dooley@...rochip.com>,
	Björn Töpel <bjorn@...osinc.com>,
	Alan Stern <stern@...land.harvard.edu>,
	Will Deacon <will@...nel.org>, Daniel Lustig <dlustig@...dia.com>,
	Brendan Sweeney <turtwig@...xas.edu>,
	Hans Boehm <hboehm@...gle.com>, Andrew Waterman <andrew@...ive.com>
Subject: Re: [RFC PATCH 0/5] RISC-V: Add dynamic TSO support

On Fri, Nov 24, 2023 at 12:04:09PM +0100, Jonas Oberhauser wrote:
> Unfortunately, at least last time I checked RISC-V still hadn't gotten such
> instructions.
> What they have is the *semantics* of the instructions, but no actual opcodes
> to encode them.
> I argued for them in the RISC-V memory group, but it was considered to be
> outside the scope of that group.

(Sorry for the late, late reply; just recalled this thread...)

That's right.  AFAICT, the discussion about the native load-acquire
and store-release instructions was revived somewhere last year within
the RVI community, culminating in the so called Zalasr-proposal [1];
Brendan, Hans and Andrew (+ Cc) might be able to provide more up-to-
date information about the status/plans for that proposal.

(Remark that RISC-V did introduce LR/SCs and AMOs instructions with
acquire/release semantics separately, cf. the so called A-extension.)

  Andrea

[1] https://github.com/mehnadnerd/riscv-zalasr