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Message-Id: <20240208124300.2740313-4-claudiu.beznea.uj@bp.renesas.com>
Date: Thu, 8 Feb 2024 14:42:46 +0200
From: Claudiu <claudiu.beznea@...on.dev>
To: geert+renesas@...der.be,
mturquette@...libre.com,
sboyd@...nel.org,
robh@...nel.org,
krzysztof.kozlowski+dt@...aro.org,
conor+dt@...nel.org,
magnus.damm@...il.com,
paul.walmsley@...ive.com,
palmer@...belt.com,
aou@...s.berkeley.edu
Cc: linux-renesas-soc@...r.kernel.org,
linux-clk@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org,
claudiu.beznea@...on.dev,
Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
Subject: [PATCH 03/17] dt-bindings: clock: r9a07g054-cpg: Add power domain IDs
From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
Add power domain IDs for RZ/V2L (R9A07G054) SoC.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
---
include/dt-bindings/clock/r9a07g054-cpg.h | 58 +++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/include/dt-bindings/clock/r9a07g054-cpg.h b/include/dt-bindings/clock/r9a07g054-cpg.h
index 43f4dbda872c..2c99f89397c4 100644
--- a/include/dt-bindings/clock/r9a07g054-cpg.h
+++ b/include/dt-bindings/clock/r9a07g054-cpg.h
@@ -226,4 +226,62 @@
#define R9A07G054_TSU_PRESETN 83
#define R9A07G054_STPAI_ARESETN 84
+/* Power domain IDs. */
+#define R9A07G054_PD_ALWAYS_ON 0
+#define R9A07G054_PD_GIC 1
+#define R9A07G054_PD_IA55 2
+#define R9A07G054_PD_MHU 3
+#define R9A07G054_PD_CORESIGHT 4
+#define R9A07G054_PD_SYC 5
+#define R9A07G054_PD_DMAC 6
+#define R9A07G054_PD_GTM0 7
+#define R9A07G054_PD_GTM1 8
+#define R9A07G054_PD_GTM2 9
+#define R9A07G054_PD_MTU 10
+#define R9A07G054_PD_POE3 11
+#define R9A07G054_PD_GPT 12
+#define R9A07G054_PD_POEGA 13
+#define R9A07G054_PD_POEGB 14
+#define R9A07G054_PD_POEGC 15
+#define R9A07G054_PD_POEGD 16
+#define R9A07G054_PD_WDT0 17
+#define R9A07G054_PD_WDT1 18
+#define R9A07G054_PD_SPI 19
+#define R9A07G054_PD_SDHI0 20
+#define R9A07G054_PD_SDHI1 21
+#define R9A07G054_PD_3DGE 22
+#define R9A07G054_PD_ISU 23
+#define R9A07G054_PD_VCPL4 24
+#define R9A07G054_PD_CRU 25
+#define R9A07G054_PD_MIPI_DSI 26
+#define R9A07G054_PD_LCDC 27
+#define R9A07G054_PD_SSI0 28
+#define R9A07G054_PD_SSI1 29
+#define R9A07G054_PD_SSI2 30
+#define R9A07G054_PD_SSI3 31
+#define R9A07G054_PD_SRC 32
+#define R9A07G054_PD_USB0 33
+#define R9A07G054_PD_USB1 34
+#define R9A07G054_PD_USB_PHY 35
+#define R9A07G054_PD_ETHER0 36
+#define R9A07G054_PD_ETHER1 37
+#define R9A07G054_PD_I2C0 38
+#define R9A07G054_PD_I2C1 39
+#define R9A07G054_PD_I2C2 40
+#define R9A07G054_PD_I2C3 41
+#define R9A07G054_PD_SCIF0 42
+#define R9A07G054_PD_SCIF1 43
+#define R9A07G054_PD_SCIF2 44
+#define R9A07G054_PD_SCIF3 45
+#define R9A07G054_PD_SCIF4 46
+#define R9A07G054_PD_SCI0 47
+#define R9A07G054_PD_SCI1 48
+#define R9A07G054_PD_IRDA 49
+#define R9A07G054_PD_RSPI0 50
+#define R9A07G054_PD_RSPI1 51
+#define R9A07G054_PD_RSPI2 52
+#define R9A07G054_PD_CANFD 53
+#define R9A07G054_PD_ADC 54
+#define R9A07G054_PD_TSU 55
+
#endif /* __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ */
--
2.39.2
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