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Message-Id: <20240208124300.2740313-17-claudiu.beznea.uj@bp.renesas.com>
Date: Thu, 8 Feb 2024 14:42:59 +0200
From: Claudiu <claudiu.beznea@...on.dev>
To: geert+renesas@...der.be,
mturquette@...libre.com,
sboyd@...nel.org,
robh@...nel.org,
krzysztof.kozlowski+dt@...aro.org,
conor+dt@...nel.org,
magnus.damm@...il.com,
paul.walmsley@...ive.com,
palmer@...belt.com,
aou@...s.berkeley.edu
Cc: linux-renesas-soc@...r.kernel.org,
linux-clk@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org,
claudiu.beznea@...on.dev,
Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
Subject: [PATCH 16/17] arm64: dts: renesas: r9a08g045: Update #power-domain-cells = <1>
From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
Update CPG #power-domain-cells = <1> and move all the IPs to be part of the
IP specific power domain as the driver has been modified to support multiple
power domains.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
---
arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index dfee878c0f49..11be621aaa82 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -62,7 +62,7 @@ scif0: serial@...4b800 {
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>;
clock-names = "fck";
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_SCIF0>;
resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>;
status = "disabled";
};
@@ -74,7 +74,7 @@ cpg: clock-controller@...10000 {
clock-names = "extal";
#clock-cells = <2>;
#reset-cells = <1>;
- #power-domain-cells = <0>;
+ #power-domain-cells = <1>;
};
sysc: system-controller@...20000 {
@@ -99,7 +99,7 @@ pinctrl: pinctrl@...30000 {
interrupt-parent = <&irqc>;
gpio-ranges = <&pinctrl 0 0 152>;
clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>;
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_ALWAYS_ON>;
resets = <&cpg R9A08G045_GPIO_RSTN>,
<&cpg R9A08G045_GPIO_PORT_RESETN>,
<&cpg R9A08G045_GPIO_SPARE_RESETN>;
@@ -168,7 +168,7 @@ irqc: interrupt-controller@...50000 {
clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>,
<&cpg CPG_MOD R9A08G045_IA55_PCLK>;
clock-names = "clk", "pclk";
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_ALWAYS_ON>;
resets = <&cpg R9A08G045_IA55_RESETN>;
};
@@ -183,7 +183,7 @@ sdhi0: mmc@...00000 {
<&cpg CPG_MOD R9A08G045_SDHI0_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
resets = <&cpg R9A08G045_SDHI0_IXRST>;
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_SDHI0>;
status = "disabled";
};
@@ -198,7 +198,7 @@ sdhi1: mmc@...10000 {
<&cpg CPG_MOD R9A08G045_SDHI1_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
resets = <&cpg R9A08G045_SDHI1_IXRST>;
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_SDHI1>;
status = "disabled";
};
@@ -213,7 +213,7 @@ sdhi2: mmc@...20000 {
<&cpg CPG_MOD R9A08G045_SDHI2_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
resets = <&cpg R9A08G045_SDHI2_IXRST>;
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_SDHI2>;
status = "disabled";
};
@@ -230,7 +230,7 @@ eth0: ethernet@...30000 {
<&cpg CPG_MOD R9A08G045_ETH0_REFCLK>;
clock-names = "axi", "chi", "refclk";
resets = <&cpg R9A08G045_ETH0_RST_HW_N>;
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_ETHER0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -249,7 +249,7 @@ eth1: ethernet@...40000 {
<&cpg CPG_MOD R9A08G045_ETH1_REFCLK>;
clock-names = "axi", "chi", "refclk";
resets = <&cpg R9A08G045_ETH1_RST_HW_N>;
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_ETHER1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -275,7 +275,7 @@ wdt0: watchdog@...00800 {
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "wdt", "perrout";
resets = <&cpg R9A08G045_WDT0_PRESETN>;
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_WDT0>;
status = "disabled";
};
};
--
2.39.2
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