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Message-ID: <3267388.oiGErgHkdL@diego>
Date: Fri, 09 Feb 2024 23:17:40 +0100
From: Heiko Stübner <heiko@...ech.de>
To: Vinod Koul <vkoul@...nel.org>, Kishon Vijay Abraham I <kishon@...nel.org>,
linux-rockchip@...ts.infradead.org, linux-phy@...ts.infradead.org,
Sebastian Reichel <sebastian.reichel@...labora.com>
Cc: Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>, Frank Wang <frank.wang@...k-chips.com>,
Kever Yang <kever.yang@...k-chips.com>, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Sebastian Reichel <sebastian.reichel@...labora.com>, kernel@...labora.com
Subject:
Re: [PATCH v1 03/10] dt-bindings: phy: add rockchip usbdp combo phy document
Hi,
Am Freitag, 9. Februar 2024, 19:17:19 CET schrieb Sebastian Reichel:
> Add device tree binding document for Rockchip USBDP Combo PHY
> with Samsung IP block.
>
> Co-developed-by: Frank Wang <frank.wang@...k-chips.com>
> Signed-off-by: Frank Wang <frank.wang@...k-chips.com>
> Signed-off-by: Sebastian Reichel <sebastian.reichel@...labora.com>
looks ok to me overall, but I stumbled over some spelling below.
> ---
> .../bindings/phy/phy-rockchip-usbdp.yaml | 166 ++++++++++++++++++
> 1 file changed, 166 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml
> new file mode 100644
> index 000000000000..3375a3099038
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml
> @@ -0,0 +1,166 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip USBDP Combo PHY with Samsung IP block
> +
> +maintainers:
> + - Frank Wang <frank.wang@...k-chips.com>
> + - Zhang Yubing <yubing.zhang@...k-chips.com>
> +
> +properties:
> + compatible:
> + enum:
> + - rockchip,rk3588-usbdp-phy
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 4
> +
> + clock-names:
> + items:
> + - const: refclk
> + - const: immortal
> + - const: pclk
> + - const: utmi
> +
> + resets:
> + maxItems: 5
> +
> + reset-names:
> + items:
> + - const: init
> + - const: cmn
> + - const: lane
> + - const: pcs_apb
> + - const: pma_apb
> +
> + rockchip,dp-lane-mux:
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + minItems: 2
> + maxItems: 4
> + description:
> + An array of physical Tyep-C lanes indexes. Position of an entry determines
nit: Type-C lane indexes
> + the dp lane index, while the value of an entry indicater physical Type-C lane.
nit: indicates instead of indicater?
> + The support dp lanes number are 2 or 4. e.g. for 2 lanes dp lanes map, we could
nit: The supported dp lane numbers ... ?
> + have "rockchip,dp-lane-mux = <2, 3>;", assuming dp lane0 on Type-C phy lane2,
> + dp lane1 on Type-C phy lane3. For 4 lanes dp lanes map, we could have
> + "rockchip,dp-lane-mux = <0, 1, 2, 3>;", assuming dp lane0 on Type-C phy lane0,
> + dp lane1 on Type-C phy lane1, dp lane2 on Type-C phy lane2, dp lane3 on Type-C
> + phy lane3. If dp lane map by DisplayPort Alt mode, this property is not need.
> +
> + rockchip,u2phy-grf:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + Phandle to the syscon managing the 'usb2 phy general register files'.
> +
> + rockchip,usb-grf:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + Phandle to the syscon managing the 'usb general register files'.
> +
> + rockchip,usbdpphy-grf:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + Phandle to the syscon managing the 'usbdp phy general register files'.
> +
> + rockchip,vo-grf:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + Phandle to the syscon managing the 'video output general register files'.
> + When select the dp lane mapping will request its phandle.
> +
> + sbu1-dc-gpios:
> + description:
> + GPIO connected to the SBU1 line of the USB-C connector via a big resistor
> + (~100K) to apply a DC offset for signalling the connector orientation.
> +
> + sbu2-dc-gpios:
> + description:
> + GPIO connected to the SBU2 line of the USB-C connector via a big resistor
> + (~100K) to apply a DC offset for signalling the connector orientation.
> +
> + orientation-switch:
> + description: Flag the port as possible handler of orientation switching
> + type: boolean
> +
> + mode-switch:
> + description: Flag the port as possible handle of altmode switching
nit: also a handler ... aka add an r ?
Heiko
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