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Message-ID: <089fd038-3019-4f6e-9a9f-47c1691a282c@oracle.com>
Date: Fri, 9 Feb 2024 09:05:53 +0000
From: Joao Martins <joao.m.martins@...cle.com>
To: Baolu Lu <baolu.lu@...ux.intel.com>, Yi Liu <yi.l.liu@...el.com>,
joro@...tes.org, jgg@...dia.com, kevin.tian@...el.com
Cc: alex.williamson@...hat.com, robin.murphy@....com, eric.auger@...hat.com,
nicolinc@...dia.com, kvm@...r.kernel.org, chao.p.peng@...ux.intel.com,
yi.y.sun@...ux.intel.com, iommu@...ts.linux.dev,
linux-kernel@...r.kernel.org, linux-kselftest@...r.kernel.org,
zhenzhong.duan@...el.com
Subject: Re: [PATCH] iommu/vt-d: Set SSADE when attaching to a parent with
dirty tracking
On 09/02/2024 02:40, Baolu Lu wrote:
> On 2024/2/8 17:14, Yi Liu wrote:
>> Should set the SSADE (Second Stage Access/Dirty bit Enable) bit of the
>> pasid entry when attaching a device to a nested domain if its parent
>> has already enabled dirty tracking.
>>
>> Fixes: 111bf85c68f6 ("iommu/vt-d: Add helper to setup pasid nested translation")
>> Signed-off-by: Yi Liu <yi.l.liu@...el.com>
>> ---
>> base commit: 547ab8fc4cb04a1a6b34377dd8fad34cd2c8a8e3
>> ---
>> drivers/iommu/intel/pasid.c | 2 ++
>> 1 file changed, 2 insertions(+)
>>
>> diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
>> index 3239cefa4c33..9be24bb762cf 100644
>> --- a/drivers/iommu/intel/pasid.c
>> +++ b/drivers/iommu/intel/pasid.c
>> @@ -658,6 +658,8 @@ int intel_pasid_setup_nested(struct intel_iommu *iommu,
>> struct device *dev,
>> pasid_set_domain_id(pte, did);
>> pasid_set_address_width(pte, s2_domain->agaw);
>> pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap));
>> + if (s2_domain->dirty_tracking)
>> + pasid_set_ssade(pte);
>> pasid_set_translation_type(pte, PASID_ENTRY_PGTT_NESTED);
>> pasid_set_present(pte);
>> spin_unlock(&iommu->lock);
>
> The same fix should also be applied to the intel_pasid_setup_second()
> path. Specifically, if a second-stage domain with dirty tracking enabled
> attaches to a device, the corresponding entry in the pasid table should
> also have the SSADE bit set.
>
I think that's already done, see below.
/*
* Set up the scalable mode pasid entry for second only translation type.
*/
int intel_pasid_setup_second_level(struct intel_iommu *iommu,
struct dmar_domain *domain,
struct device *dev, u32 pasid)
{
(...)
pasid_clear_entry(pte);
pasid_set_domain_id(pte, did);
pasid_set_slptr(pte, pgd_val);
pasid_set_address_width(pte, agaw);
pasid_set_translation_type(pte, PASID_ENTRY_PGTT_SL_ONLY);
pasid_set_fault_enable(pte);
pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap));
if (domain->dirty_tracking)
pasid_set_ssade(pte);
(...)
}
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