linux-kernel - Re: [RFC 6/7] arm64: dts: qcom: x1e80100: Enable cpufreq

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Date: Mon, 12 Feb 2024 14:58:56 +0530
From: Sibi Sankar <quic_sibis@...cinc.com>
To: Sudeep Holla <sudeep.holla@....com>
CC: <cristian.marussi@....com>, <andersson@...nel.org>,
        <konrad.dybcio@...aro.org>, <jassisinghbrar@...il.com>,
        <robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
        <linux-kernel@...r.kernel.org>, <linux-arm-msm@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <quic_rgottimu@...cinc.com>,
        <quic_kshivnan@...cinc.com>, <conor+dt@...nel.org>
Subject: Re: [RFC 6/7] arm64: dts: qcom: x1e80100: Enable cpufreq



On 1/18/24 20:55, Sudeep Holla wrote:
> (Generic note: It is middle of merge window and I have seen multiple
> series posted by you. Since I am mainly looking for bug fixes only ATM,
> I may miss to look at few. You may have to ping or repost after the merge
> window, just responding to this for now as it caught my attention)

ack

> 
> On Wed, Jan 17, 2024 at 11:04:57PM +0530, Sibi Sankar wrote:
>> Enable cpufreq on X1E80100 SoCs through the SCMI perf protocol node.
>>
>> Signed-off-by: Sibi Sankar <quic_sibis@...cinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/x1e80100.dtsi | 27 ++++++++++++++++++++++++++
>>   1 file changed, 27 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> index afdbd27f8346..6856a206f7fc 100644
>> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> @@ -62,6 +62,7 @@ CPU0: cpu@0 {
>>   			compatible = "qcom,oryon";
>>   			reg = <0x0 0x0>;
>>   			enable-method = "psci";
>> +			clocks = <&scmi_dvfs 0>;
> 
> I would use genpd bindings Ulf added recently. The reason I ask is I remember
> one of the Qcom platform had both clocks and qcom,freq-domain and each one
> served different purpose with latter one being used for cpufreq. So will
> that be an issue here ?

The cpufreq-hw node that Qualcomm used had a opp-table associated with
it to vote for various buses which in turn required both clock and freq-
domain. However the memory buses voting is done by the vendor protocol 
0x80 on X1E and hence won't be an issue here.

-Sibi

>