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Message-Id: <1c93421f-a70b-46ba-a25c-50cde87bf64d@app.fastmail.com>
Date: Tue, 13 Feb 2024 12:52:10 -0500
From: "Stefan O'Rear" <sorear@...tmail.com>
To: "Andrew Jones" <ajones@...tanamicro.com>,
"Samuel Holland" <samuel.holland@...ive.com>
Cc: "Palmer Dabbelt" <palmer@...belt.com>, linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org, stable@...r.kernel.org
Subject: Re: [PATCH -fixes v2 3/4] riscv: Add ISA extension parsing for Sm and Ss
On Tue, Feb 13, 2024, at 10:14 AM, Andrew Jones wrote:
> On Mon, Feb 12, 2024 at 07:37:34PM -0800, Samuel Holland wrote:
>> Previously, all extension version numbers were ignored. However, the
>> version number is important for these two extensions. The simplest way
>> to implement this is to use a separate bitmap bit for each supported
>> version, with each successive version implying all of the previous ones.
>> This allows alternatives and riscv_has_extension_[un]likely() to work
>> naturally.
>>
>> To avoid duplicate extensions in /proc/cpuinfo, the new successor_id
>> field allows hiding all but the newest implemented version of an
>> extension.
>>
>> Cc: <stable@...r.kernel.org> # v6.7+
>> Signed-off-by: Samuel Holland <samuel.holland@...ive.com>
>> ---
>>
>> Changes in v2:
>> - New patch for v2
>>
>> arch/riscv/include/asm/cpufeature.h | 1 +
>> arch/riscv/include/asm/hwcap.h | 8 ++++++
>> arch/riscv/kernel/cpu.c | 5 ++++
>> arch/riscv/kernel/cpufeature.c | 42 +++++++++++++++++++++++++----
>> 4 files changed, 51 insertions(+), 5 deletions(-)
>>
>> diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
>> index 0bd11862b760..ac71384e7bc4 100644
>> --- a/arch/riscv/include/asm/cpufeature.h
>> +++ b/arch/riscv/include/asm/cpufeature.h
>> @@ -61,6 +61,7 @@ struct riscv_isa_ext_data {
>> const char *property;
>> const unsigned int *subset_ext_ids;
>> const unsigned int subset_ext_size;
>> + const unsigned int successor_id;
>> };
>>
>> extern const struct riscv_isa_ext_data riscv_isa_ext[];
>> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
>> index 5340f818746b..5b51aa1db15b 100644
>> --- a/arch/riscv/include/asm/hwcap.h
>> +++ b/arch/riscv/include/asm/hwcap.h
>> @@ -80,13 +80,21 @@
>> #define RISCV_ISA_EXT_ZFA 71
>> #define RISCV_ISA_EXT_ZTSO 72
>> #define RISCV_ISA_EXT_ZACAS 73
>> +#define RISCV_ISA_EXT_SM1p11 74
>> +#define RISCV_ISA_EXT_SM1p12 75
>> +#define RISCV_ISA_EXT_SS1p11 76
>> +#define RISCV_ISA_EXT_SS1p12 77
>>
>> #define RISCV_ISA_EXT_MAX 128
>> #define RISCV_ISA_EXT_INVALID U32_MAX
>>
>> #ifdef CONFIG_RISCV_M_MODE
>> +#define RISCV_ISA_EXT_Sx1p11 RISCV_ISA_EXT_SM1p11
>> +#define RISCV_ISA_EXT_Sx1p12 RISCV_ISA_EXT_SM1p12
>> #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA
>> #else
>> +#define RISCV_ISA_EXT_Sx1p11 RISCV_ISA_EXT_SS1p11
>> +#define RISCV_ISA_EXT_Sx1p12 RISCV_ISA_EXT_SS1p12
>> #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA
>> #endif
>>
>> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
>> index d11d6320fb0d..2e6b90ed0d51 100644
>> --- a/arch/riscv/kernel/cpu.c
>> +++ b/arch/riscv/kernel/cpu.c
>> @@ -215,6 +215,11 @@ static void print_isa(struct seq_file *f, const unsigned long *isa_bitmap)
>> if (!__riscv_isa_extension_available(isa_bitmap, riscv_isa_ext[i].id))
>> continue;
>>
>> + /* Only show the newest implemented version of an extension */
>> + if (riscv_isa_ext[i].successor_id != RISCV_ISA_EXT_INVALID &&
>> + __riscv_isa_extension_available(isa_bitmap, riscv_isa_ext[i].successor_id))
>> + continue;
>
> I'm not sure we need this. Expanding Ss1p12 to 'Ss1p11 Ss1p12' and then
> outputting both in the ISA string doesn't seem harmful to me. Also, using
> a successor field instead of supersedes field may make this logic easy,
> but it'll require updating old code (changing RISCV_ISA_EXT_INVALID to the
> new version extension ID) when new versions are added. A supersedes field
> wouldn't require old code updates and would match the profiles spec which
> have explicit 'Ss1p12 supersedes Ss1p11.' type sentences.
Seconding - suppressing implied extensions in /proc/cpuinfo will require anything
that parses /proc/cpuinfo to know about extension implication in order to
generate the complete list.
>> +
>> /* Only multi-letter extensions are split by underscores */
>> if (strnlen(riscv_isa_ext[i].name, 2) != 1)
>> seq_puts(f, "_");
>> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
>> index c5b13f7dd482..8e10b50120e9 100644
>> --- a/arch/riscv/kernel/cpufeature.c
>> +++ b/arch/riscv/kernel/cpufeature.c
>> @@ -113,23 +113,29 @@ static bool riscv_isa_extension_check(int id)
>> return true;
>> }
>>
>> -#define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size) { \
>> +#define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size, _successor) { \
>> .name = #_name, \
>> .property = #_name, \
>> .id = _id, \
>> .subset_ext_ids = _subset_exts, \
>> - .subset_ext_size = _subset_exts_size \
>> + .subset_ext_size = _subset_exts_size, \
>> + .successor_id = _successor, \
>> }
>>
>> -#define __RISCV_ISA_EXT_DATA(_name, _id) _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0)
>> +#define __RISCV_ISA_EXT_DATA(_name, _id) \
>> + _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0, RISCV_ISA_EXT_INVALID)
>>
>> /* Used to declare pure "lasso" extension (Zk for instance) */
>> #define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) \
>> - _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, ARRAY_SIZE(_bundled_exts))
>> + _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, \
>> + _bundled_exts, ARRAY_SIZE(_bundled_exts), RISCV_ISA_EXT_INVALID)
>>
>> /* Used to declare extensions that are a superset of other extensions (Zvbb for instance) */
>> #define __RISCV_ISA_EXT_SUPERSET(_name, _id, _sub_exts) \
>> - _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts))
>> + _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts), RISCV_ISA_EXT_INVALID)
>> +
>> +#define __RISCV_ISA_EXT_VERSION(_name, _id, _preds, _preds_size, _successor) \
>> + _RISCV_ISA_EXT_DATA(_name, _id, _preds, _preds_size, _successor)
>>
>> static const unsigned int riscv_zk_bundled_exts[] = {
>> RISCV_ISA_EXT_ZBKB,
>> @@ -201,6 +207,16 @@ static const unsigned int riscv_zvbb_exts[] = {
>> RISCV_ISA_EXT_ZVKB
>> };
>>
>> +static const unsigned int riscv_sm_ext_versions[] = {
>> + RISCV_ISA_EXT_SM1p11,
>> + RISCV_ISA_EXT_SM1p12,
>> +};
>> +
>> +static const unsigned int riscv_ss_ext_versions[] = {
>> + RISCV_ISA_EXT_SS1p11,
>> + RISCV_ISA_EXT_SS1p12,
>> +};
>> +
>> /*
>> * The canonical order of ISA extension names in the ISA string is defined in
>> * chapter 27 of the unprivileged specification.
>> @@ -299,8 +315,16 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
>> __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH),
>> __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts),
>> __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT),
>> + __RISCV_ISA_EXT_VERSION(sm1p11, RISCV_ISA_EXT_SM1p11, riscv_sm_ext_versions, 0,
>> + RISCV_ISA_EXT_SM1p12),
>> + __RISCV_ISA_EXT_VERSION(sm1p12, RISCV_ISA_EXT_SM1p12, riscv_sm_ext_versions, 1,
>> + RISCV_ISA_EXT_INVALID),
>> __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
>> __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN),
>> + __RISCV_ISA_EXT_VERSION(ss1p11, RISCV_ISA_EXT_SS1p11, riscv_ss_ext_versions, 0,
>> + RISCV_ISA_EXT_SS1p12),
>> + __RISCV_ISA_EXT_VERSION(ss1p12, RISCV_ISA_EXT_SS1p12, riscv_ss_ext_versions, 1,
>> + RISCV_ISA_EXT_INVALID),
>> __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
>> __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
>> __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
>> @@ -414,6 +438,14 @@ static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct risc
>> ;
>>
>> ++ext_end;
>> +
>> + /*
>> + * As a special case for the Sm and Ss extensions, where the version
>> + * number is important, include it in the extension name.
>> + */
>> + if (ext_end - ext == 2 && tolower(ext[0]) == 's' &&
>> + (tolower(ext[1]) == 'm' || tolower(ext[1]) == 's'))
>> + ext_end = isa;
Per the strategy in [1] we treat every ratified version of every extension as a
unique extension; the unique aspect here is that more than one version of Sm/Ss
is defined.
[1]: https://lore.kernel.org/linux-riscv/20230608-sitting-bath-31eddc03c5a5@spud/
-s
>> break;
>> default:
>> /*
>> --
>> 2.43.0
>>
>
> Thanks,
> drew
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@...ts.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
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