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Message-ID: <20240212153625.270320718@linutronix.de>
Date: Tue, 13 Feb 2024 22:04:17 +0100 (CET)
From: Thomas Gleixner <tglx@...utronix.de>
To: LKML <linux-kernel@...r.kernel.org>
Cc: x86@...nel.org,
Tom Lendacky <thomas.lendacky@....com>,
Andrew Cooper <andrew.cooper3@...rix.com>,
Arjan van de Ven <arjan@...ux.intel.com>,
Huang Rui <ray.huang@....com>,
Juergen Gross <jgross@...e.com>,
Dimitri Sivanich <dimitri.sivanich@....com>,
Sohil Mehta <sohil.mehta@...el.com>,
K Prateek Nayak <kprateek.nayak@....com>,
Kan Liang <kan.liang@...ux.intel.com>,
Zhang Rui <rui.zhang@...el.com>,
"Paul E. McKenney" <paulmck@...nel.org>,
Feng Tang <feng.tang@...el.com>,
Andy Shevchenko <andy@...radead.org>,
Michael Kelley <mhklinux@...look.com>,
"Peter Zijlstra (Intel)" <peterz@...radead.org>,
Wang Wendy <wendy.wang@...el.com>
Subject: [patch V6 13/19] x86/mm/numa: Use core domain size on AMD
From: Thomas Gleixner <tglx@...utronix.de>
cpuinfo::topo::x86_coreid_bits is about to be phased out. Use the core
domain size from the topology information.
Add a comment why the early MPTABLE parsing is required and decrapify the
loop which sets the APIC ID to node map.
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Tested-by: Juergen Gross <jgross@...e.com>
Tested-by: Sohil Mehta <sohil.mehta@...el.com>
Tested-by: Michael Kelley <mhklinux@...look.com>
Tested-by: Zhang Rui <rui.zhang@...el.com>
Tested-by: Wang Wendy <wendy.wang@...el.com>
---
arch/x86/include/asm/topology.h | 5 +++++
arch/x86/mm/amdtopology.c | 35 ++++++++++++++++-------------------
2 files changed, 21 insertions(+), 19 deletions(-)
---
--- a/arch/x86/include/asm/topology.h
+++ b/arch/x86/include/asm/topology.h
@@ -121,6 +121,11 @@ struct x86_topology_system {
extern struct x86_topology_system x86_topo_system;
+static inline unsigned int topology_get_domain_size(enum x86_topology_domains dom)
+{
+ return x86_topo_system.dom_size[dom];
+}
+
extern const struct cpumask *cpu_coregroup_mask(int cpu);
extern const struct cpumask *cpu_clustergroup_mask(int cpu);
--- a/arch/x86/mm/amdtopology.c
+++ b/arch/x86/mm/amdtopology.c
@@ -54,13 +54,11 @@ static __init int find_northbridge(void)
int __init amd_numa_init(void)
{
- u64 start = PFN_PHYS(0);
+ unsigned int numnodes, cores, apicid;
+ u64 prevbase, start = PFN_PHYS(0);
u64 end = PFN_PHYS(max_pfn);
- unsigned numnodes;
- u64 prevbase;
- int i, j, nb;
u32 nodeid, reg;
- unsigned int bits, cores, apicid_base;
+ int i, j, nb;
if (!early_pci_allowed())
return -EINVAL;
@@ -158,26 +156,25 @@ int __init amd_numa_init(void)
return -ENOENT;
/*
- * We seem to have valid NUMA configuration. Map apicids to nodes
- * using the coreid bits from early_identify_cpu.
+ * We seem to have valid NUMA configuration. Map apicids to nodes
+ * using the size of the core domain in the APIC space.
*/
- bits = boot_cpu_data.x86_coreid_bits;
- cores = 1 << bits;
- apicid_base = 0;
+ cores = topology_get_domain_size(TOPO_CORE_DOMAIN);
/*
- * get boot-time SMP configuration:
+ * Scan MPTABLE to map the local APIC and ensure that the boot CPU
+ * APIC ID is valid. This is required because on pre ACPI/SRAT
+ * systems IO-APICs are mapped before the boot CPU.
*/
early_get_smp_config();
- if (boot_cpu_physical_apicid > 0) {
- pr_info("BSP APIC ID: %02x\n", boot_cpu_physical_apicid);
- apicid_base = boot_cpu_physical_apicid;
+ apicid = boot_cpu_physical_apicid;
+ if (apicid > 0)
+ pr_info("BSP APIC ID: %02x\n", apicid);
+
+ for_each_node_mask(i, numa_nodes_parsed) {
+ for (j = 0; j < cores; j++, apicid++)
+ set_apicid_to_node(apicid, i);
}
-
- for_each_node_mask(i, numa_nodes_parsed)
- for (j = apicid_base; j < cores + apicid_base; j++)
- set_apicid_to_node((i << bits) + j, i);
-
return 0;
}
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