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Message-ID: <20240213002416.1560357-6-jm@ti.com>
Date: Mon, 12 Feb 2024 18:24:12 -0600
From: Judith Mendez <jm@...com>
To: Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski
<krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>
CC: Nishanth Menon <nm@...com>, Vignesh Raghavendra <vigneshr@...com>,
Tero
Kristo <kristo@...nel.org>,
<linux-arm-kernel@...ts.infradead.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, Wadim Egorov
<w.egorov@...tec.de>,
Francesco Dolcini <francesco.dolcini@...adex.com>
Subject: [PATCH v2 5/9] arm64: dts: ti: k3-am62p: Add ITAP/OTAP values for MMC
Add OTAP/ITAP values to enable HS400 timing for MMC0 and
SDR104 timing for MMC1/MMC2. Remove no-1-8-v property to
enable the highest speed mode possible.
Update MMC OTAP/ITAP values according to the datasheet
[0], refer to Table 7-79 for MMC0 and Table 7-97 for MMC1/MMC2.
[0] https://www.ti.com/lit/ds/symlink/am62p.pdf
Signed-off-by: Judith Mendez <jm@...com>
---
arch/arm64/boot/dts/ti/k3-am62p-main.dtsi | 44 +++++++++++++++++++++--
arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 1 -
2 files changed, 41 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
index ef1c982a90d8..e43530beb79f 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
@@ -534,7 +534,21 @@ sdhci0: mmc@...0000 {
clock-names = "clk_ahb", "clk_xin";
assigned-clocks = <&k3_clks 57 2>;
assigned-clock-parents = <&k3_clks 57 4>;
- ti,otap-del-sel-legacy = <0x0>;
+ bus-width = <8>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ ti,clkbuf-sel = <0x7>;
+ ti,strobe-sel = <0x77>;
+ ti,trm-icp = <0x8>;
+ ti,otap-del-sel-legacy = <0x1>;
+ ti,otap-del-sel-mmc-hs = <0x1>;
+ ti,otap-del-sel-ddr52 = <0x6>;
+ ti,otap-del-sel-hs200 = <0x8>;
+ ti,otap-del-sel-hs400 = <0x5>;
+ ti,itap-del-sel-legacy = <0x10>;
+ ti,itap-del-sel-mmc-hs = <0xa>;
+ ti,itap-del-sel-ddr52 = <0x3>;
status = "disabled";
};
@@ -545,7 +559,19 @@ sdhci1: mmc@...0000 {
power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
clock-names = "clk_ahb", "clk_xin";
- ti,otap-del-sel-legacy = <0x8>;
+ bus-width = <4>;
+ ti,clkbuf-sel = <0x7>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-sd-hs = <0x0>;
+ ti,otap-del-sel-sdr12 = <0xf>;
+ ti,otap-del-sel-sdr25 = <0xf>;
+ ti,otap-del-sel-sdr50 = <0xc>;
+ ti,otap-del-sel-ddr50 = <0x9>;
+ ti,otap-del-sel-sdr104 = <0x6>;
+ ti,itap-del-sel-legacy = <0x0>;
+ ti,itap-del-sel-sd-hs = <0x0>;
+ ti,itap-del-sel-sdr12 = <0x0>;
+ ti,itap-del-sel-sdr25 = <0x0>;
status = "disabled";
};
@@ -556,7 +582,19 @@ sdhci2: mmc@...0000 {
power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 184 5>, <&k3_clks 184 6>;
clock-names = "clk_ahb", "clk_xin";
- ti,otap-del-sel-legacy = <0x8>;
+ bus-width = <4>;
+ ti,clkbuf-sel = <0x7>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-sd-hs = <0x0>;
+ ti,otap-del-sel-sdr12 = <0xf>;
+ ti,otap-del-sel-sdr25 = <0xf>;
+ ti,otap-del-sel-sdr50 = <0xc>;
+ ti,otap-del-sel-ddr50 = <0x9>;
+ ti,otap-del-sel-sdr104 = <0x6>;
+ ti,itap-del-sel-legacy = <0x0>;
+ ti,itap-del-sel-sd-hs = <0x0>;
+ ti,itap-del-sel-sdr12 = <0x0>;
+ ti,itap-del-sel-sdr25 = <0x0>;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
index 95a0146279b1..8c73587b0b62 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
@@ -424,7 +424,6 @@ &sdhci1 {
pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
disable-wp;
- no-1-8-v;
bootph-all;
};
--
2.43.0
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