[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20240214-duckbill-nimbly-4ca5ac491ec7@spud>
Date: Wed, 14 Feb 2024 18:25:11 +0000
From: Conor Dooley <conor@...nel.org>
To: Sebastian Reichel <sebastian.reichel@...labora.com>
Cc: Heiko Stuebner <heiko@...ech.de>, Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>,
linux-rockchip@...ts.infradead.org, linux-phy@...ts.infradead.org,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>,
Frank Wang <frank.wang@...k-chips.com>,
Kever Yang <kever.yang@...k-chips.com>, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, kernel@...labora.com
Subject: Re: [PATCH v2 03/12] dt-bindings: phy: add rockchip usbdp combo phy
document
On Tue, Feb 13, 2024 at 05:32:37PM +0100, Sebastian Reichel wrote:
> + rockchip,dp-lane-mux:
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + minItems: 2
> + maxItems: 4
> + description:
> + An array of physical Type-C lanes indexes. Position of an entry
> + determines the DisplayPort (DP) lane index, while the value of an entry
> + indicates physical Type-C lane. The supported DP lanes number are 2 or 4.
> + e.g. for 2 lanes DP lanes map, we could have "rockchip,dp-lane-mux = <2,
> + 3>;", assuming DP lane0 on Type-C phy lane2, DP lane1 on Type-C phy
> + lane3. For 4 lanes DP lanes map, we could have "rockchip,dp-lane-mux =
> + <0, 1, 2, 3>;", assuming DP lane0 on Type-C phy lane0, DP lane1 on Type-C
> + phy lane1, DP lane2 on Type-C phy lane2, DP lane3 on Type-C phy lane3.
> If
> + DP lane map by DisplayPort Alt mode, this property is not need.
You missed one of the nits I pointed out on the previous version:
"If DP lanes are mapped by" "not needed."
Otherwise, I think this looks okay to me..
Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>
Cheers,
Conor.
Download attachment "signature.asc" of type "application/pgp-signature" (229 bytes)
Powered by blists - more mailing lists