linux-kernel - Re: [PATCH 2/2] iio: adc: ad7944: add driver for AD7944/AD7985/AD7986

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date: Wed, 14 Feb 2024 16:13:08 +0000
From: Jonathan Cameron <Jonathan.Cameron@...wei.com>
To: David Lechner <dlechner@...libre.com>
CC: Jonathan Cameron <jic23@...nel.org>, <linux-iio@...r.kernel.org>, "Michael
 Hennerich" <Michael.Hennerich@...log.com>, Rob Herring <robh+dt@...nel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Conor Dooley
	<conor+dt@...nel.org>, Nuno Sá <nuno.sa@...log.com>, Liam
 Girdwood <lgirdwood@...il.com>, Mark Brown <broonie@...nel.org>,
	<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 2/2] iio: adc: ad7944: add driver for
 AD7944/AD7985/AD7986

On Sun, 11 Feb 2024 11:03:43 -0600
David Lechner <dlechner@...libre.com> wrote:

> On Sat, Feb 10, 2024 at 11:47 AM Jonathan Cameron <jic23@...nel.org> wrote:
> >
> > On Tue,  6 Feb 2024 11:26:00 -0600
> > David Lechner <dlechner@...libre.com> wrote:
> >  
> > > This adds a driver for the Analog Devices Inc. AD7944, AD7985, and
> > > AD7986 ADCs. These are a family of pin-compatible ADCs that can sample
> > > at rates up to 2.5 MSPS.
> > >
> > > The initial driver adds support for sampling at lower rates using the
> > > usual IIO triggered buffer and can handle all 3 possible reference
> > > voltage configurations.
> > >
> > > Signed-off-by: David Lechner <dlechner@...libre.com>  
> >
> >
> > The one thing in here that will probably bite if this gets much use of
> > different boards is the use of non multiple of 8 word sizes.
> >
> > Often we can get away with padding those with trailing clocks.
> > Any idea if that is safe here?  
> 
> We can probably get away with it on these chips. The ultimate goal
> here, though, is to get these chips working a max sample rate which
> only has a few 10s of nanoseconds of wiggle room between SPI
> transfers. So I would rather have a bit more play in the timing than
> try to support generic SPI controllers.
> 
Would just be a case of providing a fallback. If you have a good spi
controller then you get better data rats.

Meh, can be added later when someone needs this. We've done that a few
times before.

Jonathan