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Message-ID: <7a567b50-66f1-4737-ae6c-0dabd1d39bcf@quicinc.com>
Date: Thu, 15 Feb 2024 10:17:41 +0530
From: Sneh Shah <quic_snehshah@...cinc.com>
To: Jakub Kicinski <kuba@...nel.org>
CC: Vinod Koul <vkoul@...nel.org>, Bhupesh Sharma <bhupesh.sharma@...aro.org>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
Jose Abreu
<joabreu@...opsys.com>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet
<edumazet@...gle.com>, Paolo Abeni <pabeni@...hat.com>,
Maxime Coquelin
<mcoquelin.stm32@...il.com>, <netdev@...r.kernel.org>,
<linux-arm-msm@...r.kernel.org>,
<linux-stm32@...md-mailman.stormreply.com>,
<linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
<kernel@...cinc.com>, Andrew Halaney <ahalaney@...hat.com>
Subject: Re: [PATCH net-next v4] net: stmmac: dwmac-qcom-ethqos: Add support
for 2.5G SGMII
On 2/13/2024 7:00 AM, Jakub Kicinski wrote:
> On Thu, 8 Feb 2024 16:47:14 +0530 Sneh Shah wrote:
>> Serdes phy needs to operate at 2500 mode for 2.5G speed and 1000
>> mode for 1G/100M/10M speed.
>> Added changes to configure serdes phy and mac based on link speed.
>> Changing serdes phy speed involves multiple register writes for
>> serdes block. To avoid redundant write operations only update serdes
>> phy when new speed is different.
>
> Sounds like 2 separate changes in one patch, please split the
> optimization of not writing the registers multiple times and
> the 2.5G support.
>
Optimization is part of 2.5G support change only. with introduction of
2.5G speed support we need to update reconfigure serdes phy. there are
2 different serdes configs.
1. config for 2.5G
2. common config 1G/100M/10M
The change here is not to reconfigure serdes phy among
1G/100M/10M speeds and only reconfigure if it switches to 2.5G.
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
>> index 31631e3f89d0..6bbdbb7bef44 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
>> @@ -106,6 +106,7 @@ struct qcom_ethqos {
>> struct clk *link_clk;
>> struct phy *serdes_phy;
>> unsigned int speed;
>> + int serdes_speed;
>
> Why signed if speed itself is unsigned?
In stmmac speed can be assigned as SPEED_UNKNOWN which will be -1.
I will fix speed being unsigned int in a separate patch.
>
>> /* Enable and restart the Auto-Negotiation */
>> if (ane)
>> value |= GMAC_AN_CTRL_ANE | GMAC_AN_CTRL_RAN;
>> + else
>> + value &= ~GMAC_AN_CTRL_ANE;
>
> That looks unrelated. Either a separate patch or please explain in the
> commit msg why.
For 2.5G speed support MAC PCS autoneg needs to be disabled.
This adds the change to disable PCS autoneg. I will update commit
message to add more dtails
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