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Date: Thu, 15 Feb 2024 14:53:36 -0800
From: Easwar Hariharan <eahariha@...ux.microsoft.com>
To: Oliver Upton <oliver.upton@...ux.dev>
Cc: Catalin Marinas <catalin.marinas@....com>, Will Deacon <will@...nel.org>,
 Jonathan Corbet <corbet@....net>, Marc Zyngier <maz@...nel.org>,
 Andre Przywara <andre.przywara@....com>, Rob Herring <robh@...nel.org>,
 Zenghui Yu <yuzenghui@...wei.com>, Mark Rutland <mark.rutland@....com>,
 "moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)"
 <linux-arm-kernel@...ts.infradead.org>,
 "open list:DOCUMENTATION" <linux-doc@...r.kernel.org>,
 open list <linux-kernel@...r.kernel.org>,
 Anshuman Khandual <anshuman.khandual@....com>, stable@...r.kernel.org
Subject: Re: [PATCH] arm64: Subscribe Microsoft Azure Cobalt 100 to ARM
 Neoverse N2 errata

On 2/13/2024 4:19 PM, Easwar Hariharan wrote:
> On 2/12/2024 3:44 PM, Oliver Upton wrote:
>> Hi Easwar,
>>
>> On Mon, Feb 12, 2024 at 11:29:06PM +0000, Easwar Hariharan wrote:
>>> Add the MIDR value of Microsoft Azure Cobalt 100, which is a Microsoft
>>> implemented CPU based on r0p0 of the ARM Neoverse N2 CPU, and therefore
>>> suffers from all the same errata.
>>
>> Can you comment at all on where one might find this MIDR? That is, does
>> your hypervisor report the native MIDR of the implementation or does it
>> repaint it as an Arm Neoverse N2 (0x410FD490)?
> 
> We will check on the Microsoft hypervisor's plans, and get back to you.
> 
> Notwithstanding that, we do have baremetal use cases for Microsoft Azure Cobalt 100
> as well where this MIDR value will show through.
> 

<snip>

We checked in with our Microsoft hypervisor colleagues, and they do repaint the
Azure Cobalt 100 as an Arm Neoverse N2, but again, we do have baremetal use cases. 

Thanks,
Easwar


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