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Message-ID: <20240215234318.gsyjcnwnjumafg5r@synopsys.com>
Date: Thu, 15 Feb 2024 23:43:23 +0000
From: Thinh Nguyen <Thinh.Nguyen@...opsys.com>
To: Krishna Kurapati PSSNV <quic_kriskura@...cinc.com>
CC: Thinh Nguyen <Thinh.Nguyen@...opsys.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Wesley Cheng <quic_wcheng@...cinc.com>,
Konrad Dybcio <konrad.dybcio@...aro.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Conor Dooley <conor+dt@...nel.org>, Felipe Balbi <balbi@...nel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-arm-msm@...r.kernel.org" <linux-arm-msm@...r.kernel.org>,
"linux-usb@...r.kernel.org" <linux-usb@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"quic_ppratap@...cinc.com" <quic_ppratap@...cinc.com>,
"quic_jackp@...cinc.com" <quic_jackp@...cinc.com>
Subject: Re: [PATCH v14 2/9] usb: dwc3: core: Access XHCI address space
temporarily to read port info
On Fri, Feb 09, 2024, Krishna Kurapati PSSNV wrote:
>
>
> On 2/9/2024 5:12 AM, Thinh Nguyen wrote:
> > On Tue, Feb 06, 2024, Krishna Kurapati wrote:
> > > Currently Multiport DWC3 controllers are host-only capable.
> > > Temporarily map XHCI address space for host-only controllers and parse
> > > XHCI Extended Capabilities registers to read number of usb2 ports and
> > > usb3 ports present on multiport controller. Each USB Port is at least HS
> > > capable.
> > >
> > > The port info for usb2 and usb3 phy are identified as num_usb2_ports
> > > and num_usb3_ports. The intention is as follows:
> > >
> > > Wherever we need to perform phy operations like:
> > >
> > > LOOP_OVER_NUMBER_OF_AVAILABLE_PORTS()
> > > {
> > > phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
> > > phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
> > > }
> > >
> > > If number of usb2 ports is 3, loop can go from index 0-2 for
> > > usb2_generic_phy. If number of usb3-ports is 2, we don't know for sure,
> > > if the first 2 ports are SS capable or some other ports like (2 and 3)
> > > are SS capable. So instead, num_usb2_ports is used to loop around all
> > > phy's (both hs and ss) for performing phy operations. If any
> > > usb3_generic_phy turns out to be NULL, phy operation just bails out.
> > > num_usb3_ports is used to modify GUSB3PIPECTL registers while setting up
> > > phy's as we need to know how many SS capable ports are there for this.
> > >
> > > Signed-off-by: Krishna Kurapati <quic_kriskura@...cinc.com>
> > > ---
> > > drivers/usb/dwc3/core.c | 62 +++++++++++++++++++++++++++++++++++++++++
> > > drivers/usb/dwc3/core.h | 5 ++++
> > > 2 files changed, 67 insertions(+)
> > >
> > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > > index 3b68e8e45b8b..965eaad195fb 100644
> > > --- a/drivers/usb/dwc3/core.c
> > > +++ b/drivers/usb/dwc3/core.c
> > > @@ -39,6 +39,7 @@
> > > #include "io.h"
> > > #include "debug.h"
> > > +#include "../host/xhci-ext-caps.h"
> > > #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
> > > @@ -1882,10 +1883,57 @@ static int dwc3_get_clocks(struct dwc3 *dwc)
> > > return 0;
> > > }
> > > +static int dwc3_read_port_info(struct dwc3 *dwc)
> >
> > I think it may fit better to leave this function definition in host.c.
> > But you can also argue to leave it here. Let me know what you think.
>
> I'd like to keep it here for now.
>
> >
> > > +{
> > > + void __iomem *base;
> > > + u8 major_revision;
> > > + u32 offset;
> > > + u32 val;
> > > +
> > > + /*
> > > + * Remap xHCI address space to access XHCI ext cap regs since it is
> > > + * needed to get information on number of ports present.
> > > + */
> > > + base = ioremap(dwc->xhci_resources[0].start,
> > > + resource_size(&dwc->xhci_resources[0]));
> > > + if (IS_ERR(base))
> >
> > ioremap returns NULL on errors.
> >
>
> Can we keep the above for now if the v14 series goes well. I'll post a patch
> later for this. Incase it turns out I need v15 I will make this change in
> v15.
Sure. It's a minor issue and shouldn't hold back this series.
>
> > > + return PTR_ERR(base);
> > > +
> > > + offset = 0;
> > > + do {
> > > + offset = xhci_find_next_ext_cap(base, offset,
> > > + XHCI_EXT_CAPS_PROTOCOL);
> > > + if (!offset)
> > > + break;
> > > +
> > > + val = readl(base + offset);
> > > + major_revision = XHCI_EXT_PORT_MAJOR(val);
> > > +
> > > + val = readl(base + offset + 0x08);
> > > + if (major_revision == 0x03) {
> > > + dwc->num_usb3_ports += XHCI_EXT_PORT_COUNT(val);
> > > + } else if (major_revision <= 0x02) {
> > > + dwc->num_usb2_ports += XHCI_EXT_PORT_COUNT(val);
> > > + } else {
> > > + dev_warn(dwc->dev,
> > > + "unrecognized port major revision %d\n",
> > > + major_revision);
> > > + }
> > > + } while (1);
> > > +
> > > + dev_dbg(dwc->dev, "hs-ports: %u ss-ports: %u\n",
> > > + dwc->num_usb2_ports, dwc->num_usb3_ports);
> > > +
> > > + iounmap(base);
> > > +
> > > + return 0;
> > > +}
> > > +
> >
> > > static int dwc3_probe(struct platform_device *pdev)
> > > {
> > > struct device *dev = &pdev->dev;
> > > struct resource *res, dwc_res;
> > > + unsigned int hw_mode;
> > > void __iomem *regs;
> > > struct dwc3 *dwc;
> > > int ret;
> > > @@ -1969,6 +2017,20 @@ static int dwc3_probe(struct platform_device *pdev)
> > > goto err_disable_clks;
> > > }
> > > + /*
> > > + * Currently only DWC3 controllers that are host-only capable
> > > + * support Multiport.
> > > + */
> > > + hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
> > > + if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) {
> > > + ret = dwc3_read_port_info(dwc);
> >
> > The function name here can be reworded as it does more than reading the
> > port info. Perhaps dwc3_get_num_ports()?
> >
> I am fine either ways. I'll change the func name in v15.
>
Acked-by: Thinh Nguyen <Thinh.Nguyen@...opsys.com>
Thanks,
Thinh
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