[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Message-ID: <d0f251f4-1c9e-4ed2-b7df-5a7fda28fe4e@siemens.com>
Date: Thu, 15 Feb 2024 09:14:47 +0100
From: Jan Kiszka <jan.kiszka@...mens.com>
To: Conor Dooley <conor+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>
Cc: "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
devicetree <devicetree@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Kishon Vijay Abraham I <kishon@...com>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>, Rob Herring
<robh@...nel.org>, Nishanth Menon <nm@...com>, "Andrew F. Davis"
<afd@...com>, Bjorn Helgaas <bhelgaas@...gle.com>,
"Lopes Ivo, Diogo Miguel (T CED IFD-PT)" <diogo.ivo@...mens.com>
Subject: [PATCH] dt-bindings: PCI: ti,am65: Fix remaining binding warnings
From: Jan Kiszka <jan.kiszka@...mens.com>
This adds the missing num-viewport, phys and phy-name properties to the
schema. Based on driver code, num-viewport is required for the root
complex, phys are optional. Their number corresponds to the number of
lanes. The AM65x supports up to 2 lanes.
Signed-off-by: Jan Kiszka <jan.kiszka@...mens.com>
---
.../bindings/pci/ti,am65-pci-host.yaml | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml
index a20dccbafd94..cdd6834f6a6f 100644
--- a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml
+++ b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml
@@ -55,6 +55,20 @@ properties:
dma-coherent: true
+ num-viewport:
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ phys:
+ description: per-lane PHYs
+ minItems: 1
+ maxItems: 2
+
+ phy-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ pattern: '^pcie-phy[0-9]+$'
+
required:
- compatible
- reg
@@ -74,6 +88,7 @@ then:
- dma-coherent
- power-domains
- msi-map
+ - num-viewport
unevaluatedProperties: false
@@ -98,9 +113,13 @@ examples:
ti,syscon-pcie-id = <&scm_conf 0x0210>;
ti,syscon-pcie-mode = <&scm_conf 0x4060>;
bus-range = <0x0 0xff>;
+ num-viewport = <16>;
max-link-speed = <2>;
dma-coherent;
interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
msi-map = <0x0 &gic_its 0x0 0x10000>;
device_type = "pci";
+ num-lanes = <1>;
+ phys = <&serdes0 PHY_TYPE_PCIE 0>;
+ phy-names = "pcie-phy0";
};
--
2.35.3
Powered by blists - more mailing lists