linux-kernel - Re: [PATCH v3 2/4] reset: simple: add support for Sophgo SG2042

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID:
 <MA0P287MB2822E03B61DF33B4438833D9FE4D2@MA0P287MB2822.INDP287.PROD.OUTLOOK.COM>
Date: Thu, 15 Feb 2024 16:59:07 +0800
From: Chen Wang <unicorn_wang@...look.com>
To: Chen Wang <unicornxw@...il.com>, aou@...s.berkeley.edu,
 chao.wei@...hgo.com, conor@...nel.org, krzysztof.kozlowski+dt@...aro.org,
 palmer@...belt.com, paul.walmsley@...ive.com, p.zabel@...gutronix.de,
 robh+dt@...nel.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
 haijiao.liu@...hgo.com, xiaoguang.xing@...hgo.com, guoren@...nel.org,
 jszhang@...nel.org, inochiama@...look.com
Subject: Re: [PATCH v3 2/4] reset: simple: add support for Sophgo SG2042

ping ~~~

On 2024/1/30 9:50, Chen Wang wrote:
> From: Chen Wang <unicorn_wang@...look.com>
>
> Reuse reset-simple driver for the Sophgo SG2042 reset generator.
>
> Signed-off-by: Chen Wang <unicorn_wang@...look.com>
> ---
>   drivers/reset/Kconfig        | 3 ++-
>   drivers/reset/reset-simple.c | 2 ++
>   2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index ccd59ddd7610..2034f69d5953 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -213,7 +213,7 @@ config RESET_SCMI
>   
>   config RESET_SIMPLE
>   	bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT
> -	default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC
> +	default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_SOPHGO || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC
>   	depends on HAS_IOMEM
>   	help
>   	  This enables a simple reset controller driver for reset lines that
> @@ -228,6 +228,7 @@ config RESET_SIMPLE
>   	   - RCC reset controller in STM32 MCUs
>   	   - Allwinner SoCs
>   	   - SiFive FU740 SoCs
> +	   - Sophgo SoCs
>   
>   config RESET_SOCFPGA
>   	bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA)
> diff --git a/drivers/reset/reset-simple.c b/drivers/reset/reset-simple.c
> index 818cabcc9fb7..276067839830 100644
> --- a/drivers/reset/reset-simple.c
> +++ b/drivers/reset/reset-simple.c
> @@ -151,6 +151,8 @@ static const struct of_device_id reset_simple_dt_ids[] = {
>   	{ .compatible = "snps,dw-high-reset" },
>   	{ .compatible = "snps,dw-low-reset",
>   		.data = &reset_simple_active_low },
> +	{ .compatible = "sophgo,sg2042-reset",
> +		.data = &reset_simple_active_low },
>   	{ /* sentinel */ },
>   };
>   

hello,  Philipp,

Can you please have a look of this, I have fixed the issue you raised in 
last version, any question please feel free let me know.

BTW, will you pick this for v6.9 if it is ok to you.

Thanks,

Chen