linux-kernel - Re: [PATCH V16 13/13] PCI: tegra: Add Tegra194 PCIe support

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Date: Thu, 15 Feb 2024 16:55:47 +0530
From: Vidya Sagar <vidyas@...dia.com>
To: Bjorn Helgaas <helgaas@...nel.org>
Cc: Lorenzo Pieralisi <lpieralisi@...nel.org>, bhelgaas@...gle.com,
 robh+dt@...nel.org, mark.rutland@....com, thierry.reding@...il.com,
 jonathanh@...dia.com, Kishon Vijay Abraham I <kishon@...nel.org>,
 catalin.marinas@....com, Will Deacon <will@...nel.org>,
 jingoohan1@...il.com, gustavo.pimentel@...opsys.com, digetx@...il.com,
 mperttunen@...dia.com, linux-pci@...r.kernel.org,
 devicetree@...r.kernel.org, linux-tegra@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 kthota@...dia.com, mmaddireddy@...dia.com, sagar.tv@...il.com
Subject: Re: [PATCH V16 13/13] PCI: tegra: Add Tegra194 PCIe support


On 15-02-2024 00:42, Bjorn Helgaas wrote:
> External email: Use caution opening links or attachments
>
>
> Hi Vidya, question about ancient history:
>
> On Tue, Aug 13, 2019 at 05:06:27PM +0530, Vidya Sagar wrote:
>> Add support for Synopsys DesignWare core IP based PCIe host controller
>> present in Tegra194 SoC.
>> ...
>> +static int tegra_pcie_dw_host_init(struct pcie_port *pp)
>> +{
>> +     struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>> +     struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
>> +     u32 val, tmp, offset, speed;
>> +
>> +     tegra_pcie_prepare_host(pp);
>> +
>> +     if (dw_pcie_wait_for_link(pci)) {
>> +             /*
>> +              * There are some endpoints which can't get the link up if
>> +              * root port has Data Link Feature (DLF) enabled.
>> +              * Refer Spec rev 4.0 ver 1.0 sec 3.4.2 & 7.7.4 for more info
>> +              * on Scaled Flow Control and DLF.
>> +              * So, need to confirm that is indeed the case here and attempt
>> +              * link up once again with DLF disabled.
> This comment suggests that there's an issue with *Endpoints*, not an
> issue with the Root Port.  If so, it seems like this problem could
> occur with all Root Ports, not just Tegra194.  Do you remember any
> details about this?
>
> I don't remember hearing about any similar issues, and this driver is
> the only place PCI_EXT_CAP_ID_DLF is referenced, so maybe it is
> actually something related to Tegra194?
We noticed PCIe link-up issues with some endpoints. link-up at the physical
layer level but NOT at the Data link layer level precisely. We further
figured out that it is the DLFE DLLPs that the root port sends during the
link up process which are causing the endpoints get confused and preventing
them from sending the InitFC DLLPs leading to the link not being up at
Data Link Layer level.

PCIe spec rev4.0, Rev 4.0, ver 1.0, Section-3.3 says that (verbatim) 
"The Data
Link Feature Exchange Enable field permits systems to disable the Data Link
Feature Exchange. This can be used to work around legacy hardware that does
not correctly ignore the DLLP".

Based on this, we added the following code to retry link-up with DLFE 
disabled,
only upon confirming that the link came up at phy level but not at the 
DL level
in the previous attempt.

Thanks,

Vidya Sagar

>
>> +             val = appl_readl(pcie, APPL_DEBUG);
>> +             val &= APPL_DEBUG_LTSSM_STATE_MASK;
>> +             val >>= APPL_DEBUG_LTSSM_STATE_SHIFT;
>> +             tmp = appl_readl(pcie, APPL_LINK_STATUS);
>> +             tmp &= APPL_LINK_STATUS_RDLH_LINK_UP;
>> +             if (!(val == 0x11 && !tmp)) {
>> +                     /* Link is down for all good reasons */
>> +                     return 0;
>> +             }
>> +
>> +             dev_info(pci->dev, "Link is down in DLL");
>> +             dev_info(pci->dev, "Trying again with DLFE disabled\n");
>> +             /* Disable LTSSM */
>> +             val = appl_readl(pcie, APPL_CTRL);
>> +             val &= ~APPL_CTRL_LTSSM_EN;
>> +             appl_writel(pcie, val, APPL_CTRL);
>> +
>> +             reset_control_assert(pcie->core_rst);
>> +             reset_control_deassert(pcie->core_rst);
>> +
>> +             offset = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_DLF);
>> +             val = dw_pcie_readl_dbi(pci, offset + PCI_DLF_CAP);
>> +             val &= ~PCI_DLF_EXCHANGE_ENABLE;
>> +             dw_pcie_writel_dbi(pci, offset, val);
>> +
>> +             tegra_pcie_prepare_host(pp);
>> +
>> +             if (dw_pcie_wait_for_link(pci))
>> +                     return 0;
>> +     }
>> +
>> +     speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) &
>> +             PCI_EXP_LNKSTA_CLS;
>> +     clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]);
>> +
>> +     tegra_pcie_enable_interrupts(pp);
>> +
>> +     return 0;
>> +}