linux-kernel - RE: [PATCH v8 0/3] Add ECC feature support to Tx and Rx FIFOs for Xilinx CAN Controller.

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Date: Thu, 15 Feb 2024 13:59:33 +0000
From: "Goud, Srinivas" <srinivas.goud@....com>
To: Marc Kleine-Budde <mkl@...gutronix.de>, Appana Durga Kedareswara rao
	<appana.durga.rao@...inx.com>, Naga Sureshkumar Relli
	<naga.sureshkumar.relli@...inx.com>, Wolfgang Grandegger <wg@...ndegger.com>,
	"David S. Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, Rob
 Herring <robh+dt@...nel.org>, Krzysztof Kozlowski
	<krzysztof.kozlowski+dt@...aro.org>, Conor Dooley <conor+dt@...nel.org>,
	"Simek, Michal" <michal.simek@....com>
CC: "linux-can@...r.kernel.org" <linux-can@...r.kernel.org>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>, Conor Dooley <conor.dooley@...rochip.com>
Subject: RE: [PATCH v8 0/3] Add ECC feature support to Tx and Rx FIFOs for
 Xilinx CAN Controller.

Hi Marc,

>-----Original Message-----
>From: Marc Kleine-Budde <mkl@...gutronix.de>
>Sent: Tuesday, February 13, 2024 4:07 PM
>To: Appana Durga Kedareswara rao <appana.durga.rao@...inx.com>; Naga
>Sureshkumar Relli <naga.sureshkumar.relli@...inx.com>; Wolfgang Grandegger
><wg@...ndegger.com>; Marc Kleine-Budde <mkl@...gutronix.de>; David S.
>Miller <davem@...emloft.net>; Eric Dumazet <edumazet@...gle.com>;
>Jakub Kicinski <kuba@...nel.org>; Paolo Abeni <pabeni@...hat.com>; Rob
>Herring <robh+dt@...nel.org>; Krzysztof Kozlowski
><krzysztof.kozlowski+dt@...aro.org>; Conor Dooley <conor+dt@...nel.org>;
>Simek, Michal <michal.simek@....com>
>Cc: linux-can@...r.kernel.org; netdev@...r.kernel.org;
>devicetree@...r.kernel.org; linux-arm-kernel@...ts.infradead.org; linux-
>kernel@...r.kernel.org; Goud, Srinivas <srinivas.goud@....com>; Conor
>Dooley <conor.dooley@...rochip.com>
>Subject: [PATCH v8 0/3] Add ECC feature support to Tx and Rx FIFOs for Xilinx
>CAN Controller.
>
>ECC is an IP configuration option where counter registers are added in IP for
>1bit/2bit ECC errors count and reset.
>
>Also driver reports 1bit/2bit ECC errors for FIFOs based on ECC error interrupts.
>
>Add xlnx,has-ecc optional property for Xilinx AXI CAN controller to support ECC
>if the ECC block is enabled in the HW.
>
>Add ethtool stats interface for getting all the ECC errors information.
>
>There is no public documentation for it available.
>
>Changes in v8:
>- Use u64_stats_sync instead of spinlock
>- Renamed stats strings: use "_" instead of "-"
>- Renamed stats strings: add "_errors" trailer
>- Renamed stats variables similar to stats strings
>
>Changes in v7:
>- Update with spinlock only for stats counters
>
>Changes in v6:
>- Update commit description
>
>Changes in v5:
>- Fix review comments
>- Change the sequence of updates the stats
>- Add get_strings and get_sset_count stats interface
>- Use u64 stats helper function
>
>Changes in v4:
>- Fix DT binding check warning
>- Update xlnx,has-ecc property description
>
>Changes in v3:
>- Update mailing list
>- Update commit description
>
>Changes in v2:
>- Address review comments
>- Add ethtool stats interface
>- Update commit description
>
>---
>Srinivas Goud (3):
>      dt-bindings: can: xilinx_can: Add 'xlnx,has-ecc' optional property
>      can: xilinx_can: Add ECC support
>      can: xilinx_can: Add ethtool stats interface for ECC errors
>
> .../devicetree/bindings/net/can/xilinx,can.yaml    |   5 +
> drivers/net/can/xilinx_can.c                       | 169 ++++++++++++++++++++-
> 2 files changed, 170 insertions(+), 4 deletions(-)
>---
>base-commit: a3522a2edb3faf8cb98d38c2a99f5967beef24e2
>change-id: 20240213-xilinx_ecc-8310f5556010
>
>Best regards,
>--
>Marc Kleine-Budde <mkl@...gutronix.de>
>

Thanks, tested with v8 changes, it is working fine.

Thanks,
Srinivas