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Date: Fri, 16 Feb 2024 13:04:25 +0100
From: Johan Hovold <johan@...nel.org>
To: Konrad Dybcio <konrad.dybcio@...aro.org>
Cc: Johan Hovold <johan+linaro@...nel.org>,
	Bjorn Andersson <andersson@...nel.org>,
	Bjorn Helgaas <bhelgaas@...gle.com>,
	Lorenzo Pieralisi <lpieralisi@...nel.org>,
	Krzysztof WilczyƄski <kw@...ux.com>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
	linux-arm-msm@...r.kernel.org, linux-pci@...r.kernel.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 04/10] arm64: dts: qcom: sc8280xp-crd: limit pcie4 link
 speed

On Fri, Feb 16, 2024 at 08:12:46AM +0100, Johan Hovold wrote:
> On Thu, Feb 15, 2024 at 09:47:01PM +0100, Konrad Dybcio wrote:
> > On 12.02.2024 17:50, Johan Hovold wrote:
> > > Limit the WiFi PCIe link speed to Gen2 speed (500 GB/s), which is the
> > 
> > MB/s
> 
> Indeed, thanks for spotting that.
> 
> > > speed that Windows uses.

> > Hm.. I'dve assumed it ships with a WLAN card that supports moving
> > more bandwidth.. Is it always at gen2?

> But yes, it seems we may be limiting the theoretical maximum data rate
> for the wifi this way.

It looks like the peak wifi speed for these chips is 3.6 Gbps, and it
may be lower for the X13s (and in practice). So 500 MB/s should be more
than enough.

	https://www.qualcomm.com/products/technology/wi-fi/fastconnect/fastconnect-6900

Johan

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