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Date: Thu, 15 Feb 2024 16:08:17 -0800
From: Samuel Holland <samuel.holland@...ive.com>
To: Will Deacon <will@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Eric Lin <eric.lin@...ive.com>,
Conor Dooley <conor@...nel.org>
Cc: Palmer Dabbelt <palmer@...belt.com>,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Paul Walmsley <paul.walmsley@...ive.com>,
linux-riscv@...ts.infradead.org,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
linux-arm-kernel@...ts.infradead.org,
Samuel Holland <samuel.holland@...ive.com>
Subject: [PATCH v1 5/6] dt-bindings: cache: Add SiFive Private L2 Cache controller
From: Eric Lin <eric.lin@...ive.com>
Add YAML DT binding documentation for the SiFive Private L2 Cache
controller. Some functionality and the corresponding register bits were
removed in the sifive,pl2cache1 version of the hardware, which creates
the unusual situation where the newer hardware's compatible string is
the fallback for the older one.
Signed-off-by: Eric Lin <eric.lin@...ive.com>
Co-developed-by: Samuel Holland <samuel.holland@...ive.com>
Signed-off-by: Samuel Holland <samuel.holland@...ive.com>
---
Changes in v1:
- Add back select: clause to binding
- Make sifive,pl2cache1 the fallback for sifive,pl2cache0
- Fix the order of the reg property declaration
- Document the sifive,perfmon-counters property
.../bindings/cache/sifive,pl2cache0.yaml | 81 +++++++++++++++++++
1 file changed, 81 insertions(+)
create mode 100644 Documentation/devicetree/bindings/cache/sifive,pl2cache0.yaml
diff --git a/Documentation/devicetree/bindings/cache/sifive,pl2cache0.yaml b/Documentation/devicetree/bindings/cache/sifive,pl2cache0.yaml
new file mode 100644
index 000000000000..d89e2e5d0a97
--- /dev/null
+++ b/Documentation/devicetree/bindings/cache/sifive,pl2cache0.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (C) 2023-2024 SiFive, Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/cache/sifive,pl2cache0.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SiFive Private L2 Cache Controller
+
+maintainers:
+ - Eric Lin <eric.lin@...ive.com>
+
+description:
+ The SiFive Private L2 Cache Controller is a per-core cache which communicates
+ with both the upstream L1 caches and downstream L3 cache or memory, enabling a
+ high-performance cache subsystem.
+
+allOf:
+ - $ref: /schemas/cache-controller.yaml#
+
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - sifive,pl2cache1
+
+ required:
+ - compatible
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: sifive,pl2cache0
+ - const: sifive,pl2cache1
+ - const: cache
+ - items:
+ - const: sifive,pl2cache1
+ - const: cache
+
+ reg:
+ maxItems: 1
+
+ cache-block-size: true
+ cache-level: true
+ cache-sets: true
+ cache-size: true
+ cache-unified: true
+
+ next-level-cache: true
+
+ sifive,perfmon-counters:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+ description: Number of PMU counter registers
+
+required:
+ - compatible
+ - reg
+ - cache-block-size
+ - cache-level
+ - cache-sets
+ - cache-size
+ - cache-unified
+
+additionalProperties: false
+
+examples:
+ - |
+ cache-controller@...04000 {
+ compatible = "sifive,pl2cache1", "cache";
+ reg = <0x10104000 0x4000>;
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <512>;
+ cache-size = <262144>;
+ cache-unified;
+ next-level-cache = <&L4>;
+ sifive,perfmon-counters = <6>;
+ };
--
2.43.0
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