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Message-Id: <20240217-hisi-wdt-v1-2-cdb9ddcab968@outlook.com>
Date: Sat, 17 Feb 2024 12:40:35 +0800
From: Yang Xiwen via B4 Relay <devnull+forbidden405.outlook.com@...nel.org>
To: Wim Van Sebroeck <wim@...ux-watchdog.org>, 
 Guenter Roeck <linux@...ck-us.net>, Philipp Zabel <p.zabel@...gutronix.de>, 
 Rob Herring <robh+dt@...nel.org>, 
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, 
 Conor Dooley <conor+dt@...nel.org>, Viresh Kumar <vireshk@...nel.org>
Cc: linux-watchdog@...r.kernel.org, linux-kernel@...r.kernel.org, 
 devicetree@...r.kernel.org, Yang Xiwen <forbidden405@...look.com>
Subject: [PATCH 2/2] dt-binding: watchdog: arm,sp805: document the reset
 signal

From: Yang Xiwen <forbidden405@...look.com>

The reset signal needs to be deasserted before operation of sp805
module. Document in the binding.

Signed-off-by: Yang Xiwen <forbidden405@...look.com>
---
 Documentation/devicetree/bindings/watchdog/arm,sp805.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/watchdog/arm,sp805.yaml b/Documentation/devicetree/bindings/watchdog/arm,sp805.yaml
index 7aea255b301b..6d4f63f23f1a 100644
--- a/Documentation/devicetree/bindings/watchdog/arm,sp805.yaml
+++ b/Documentation/devicetree/bindings/watchdog/arm,sp805.yaml
@@ -50,6 +50,11 @@ properties:
       - const: wdog_clk
       - const: apb_pclk
 
+  resets:
+    maxItems: 1
+    description: |
+      WDOGRESn input reset signal for sp805 module.
+
 required:
   - compatible
   - reg
@@ -67,4 +72,5 @@ examples:
         interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
         clocks = <&wdt_clk>, <&apb_pclk>;
         clock-names = "wdog_clk", "apb_pclk";
+        resets = <&wdt_rst>;
     };

-- 
2.43.0


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