linux-kernel - [PATCH RFC 05/20] RISC-V: Define indirect CSR access helpers

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Message-Id: <20240217005738.3744121-6-atishp@rivosinc.com>
Date: Fri, 16 Feb 2024 16:57:23 -0800
From: Atish Patra <atishp@...osinc.com>
To: linux-kernel@...r.kernel.org
Cc: Atish Patra <atishp@...osinc.com>,
	Adrian Hunter <adrian.hunter@...el.com>,
	Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
	Alexandre Ghiti <alexghiti@...osinc.com>,
	Andrew Jones <ajones@...tanamicro.com>,
	Anup Patel <anup@...infault.org>,
	Arnaldo Carvalho de Melo <acme@...nel.org>,
	Atish Patra <atishp@...shpatra.org>,
	Christian Brauner <brauner@...nel.org>,
	Clément Léger <cleger@...osinc.com>,
	Conor Dooley <conor@...nel.org>,
	devicetree@...r.kernel.org,
	Evan Green <evan@...osinc.com>,
	Guo Ren <guoren@...nel.org>,
	Heiko Stuebner <heiko@...ech.de>,
	Ian Rogers <irogers@...gle.com>,
	Ingo Molnar <mingo@...hat.com>,
	James Clark <james.clark@....com>,
	Jing Zhang <renyu.zj@...ux.alibaba.com>,
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	Ji Sheng Teoh <jisheng.teoh@...rfivetech.com>,
	John Garry <john.g.garry@...cle.com>,
	Jonathan Corbet <corbet@....net>,
	Kan Liang <kan.liang@...ux.intel.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
	kvm-riscv@...ts.infradead.org,
	kvm@...r.kernel.org,
	Ley Foon Tan <leyfoon.tan@...rfivetech.com>,
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	Yang Jihong <yangjihong1@...wei.com>
Subject: [PATCH RFC 05/20] RISC-V: Define indirect CSR access helpers

The indriect CSR requires multiple instructions to read/write CSR.
Add a few helper functions for ease of usage.

Signed-off-by: Atish Patra <atishp@...osinc.com>
---
 arch/riscv/include/asm/csr_ind.h | 42 ++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100644 arch/riscv/include/asm/csr_ind.h

diff --git a/arch/riscv/include/asm/csr_ind.h b/arch/riscv/include/asm/csr_ind.h
new file mode 100644
index 000000000000..9611c221eb6f
--- /dev/null
+++ b/arch/riscv/include/asm/csr_ind.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2024 Rivos Inc.
+ */
+
+#ifndef _ASM_RISCV_CSR_IND_H
+#define _ASM_RISCV_CSR_IND_H
+
+#include <asm/csr.h>
+
+#define csr_ind_read(iregcsr, iselbase, iseloff) ({	\
+	unsigned long value = 0;			\
+	unsigned long flags;				\
+	local_irq_save(flags);				\
+	csr_write(CSR_ISELECT, iselbase + iseloff);	\
+	value = csr_read(iregcsr);			\
+	local_irq_restore(flags);			\
+	value;						\
+})
+
+#define csr_ind_write(iregcsr, iselbase, iseloff, value) ({	\
+	unsigned long flags;					\
+	local_irq_save(flags);					\
+	csr_write(CSR_ISELECT, iselbase + iseloff);		\
+	csr_write(iregcsr, value);				\
+	local_irq_restore(flags);				\
+})
+
+#define csr_ind_warl(iregcsr, iselbase, iseloff, warl_val) ({	\
+	unsigned long old_val = 0, value = 0;			\
+	unsigned long flags;					\
+	local_irq_save(flags);					\
+	csr_write(CSR_ISELECT, iselbase + iseloff);		\
+	old_val = csr_read(iregcsr);				\
+	csr_write(iregcsr, value);				\
+	value = csr_read(iregcsr);				\
+	csr_write(iregcsr, old_val);				\
+	local_irq_restore(flags);				\
+	value;							\
+})
+
+#endif
-- 
2.34.1