linux-kernel - [PATCH RFC 09/20] RISC-V: Add Smcntrpmf extension parsing

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Message-Id: <20240217005738.3744121-10-atishp@rivosinc.com>
Date: Fri, 16 Feb 2024 16:57:27 -0800
From: Atish Patra <atishp@...osinc.com>
To: linux-kernel@...r.kernel.org
Cc: Atish Patra <atishp@...osinc.com>,
	Adrian Hunter <adrian.hunter@...el.com>,
	Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
	Alexandre Ghiti <alexghiti@...osinc.com>,
	Andrew Jones <ajones@...tanamicro.com>,
	Anup Patel <anup@...infault.org>,
	Arnaldo Carvalho de Melo <acme@...nel.org>,
	Atish Patra <atishp@...shpatra.org>,
	Christian Brauner <brauner@...nel.org>,
	Clément Léger <cleger@...osinc.com>,
	Conor Dooley <conor@...nel.org>,
	devicetree@...r.kernel.org,
	Evan Green <evan@...osinc.com>,
	Guo Ren <guoren@...nel.org>,
	Heiko Stuebner <heiko@...ech.de>,
	Ian Rogers <irogers@...gle.com>,
	Ingo Molnar <mingo@...hat.com>,
	James Clark <james.clark@....com>,
	Jing Zhang <renyu.zj@...ux.alibaba.com>,
	Jiri Olsa <jolsa@...nel.org>,
	Ji Sheng Teoh <jisheng.teoh@...rfivetech.com>,
	John Garry <john.g.garry@...cle.com>,
	Jonathan Corbet <corbet@....net>,
	Kan Liang <kan.liang@...ux.intel.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
	kvm-riscv@...ts.infradead.org,
	kvm@...r.kernel.org,
	Ley Foon Tan <leyfoon.tan@...rfivetech.com>,
	linux-doc@...r.kernel.org,
	linux-perf-users@...r.kernel.org,
	linux-riscv@...ts.infradead.org,
	Mark Rutland <mark.rutland@....com>,
	Namhyung Kim <namhyung@...nel.org>,
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	Peter Zijlstra <peterz@...radead.org>,
	Rob Herring <robh+dt@...nel.org>,
	Samuel Holland <samuel.holland@...ive.com>,
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	Will Deacon <will@...nel.org>,
	kaiwenxue1@...il.com,
	Yang Jihong <yangjihong1@...wei.com>
Subject: [PATCH RFC 09/20] RISC-V: Add Smcntrpmf extension parsing

Smcntrpmf extension allows M-mode to enable privilege mode filtering
for cycle/instret counters. However, the cyclecfg/instretcfg CSRs are
only available only in Ssccfg only Smcntrpmf is present.

That's why, kernel needs to detect presence of Smcntrpmf extension and
enable privilege mode filtering for cycle/instret counters.

Signed-off-by: Atish Patra <atishp@...osinc.com>
---
 arch/riscv/include/asm/hwcap.h | 1 +
 arch/riscv/kernel/cpufeature.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 5f4401e221ee..b82a8d7a9b3b 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -84,6 +84,7 @@
 #define RISCV_ISA_EXT_SMCSRIND		75
 #define RISCV_ISA_EXT_SSCCFG            76
 #define RISCV_ISA_EXT_SMCDELEG          77
+#define RISCV_ISA_EXT_SMCNTRPMF         78
 
 #define RISCV_ISA_EXT_MAX		128
 #define RISCV_ISA_EXT_INVALID		U32_MAX
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 77cc5dbd73bf..c30be2c924e7 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -302,6 +302,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
 	__RISCV_ISA_EXT_DATA(smcdeleg, RISCV_ISA_EXT_SMCDELEG),
 	__RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN),
+	__RISCV_ISA_EXT_DATA(smcntrpmf, RISCV_ISA_EXT_SMCNTRPMF),
 	__RISCV_ISA_EXT_DATA(smcsrind, RISCV_ISA_EXT_SMCSRIND),
 	__RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
 	__RISCV_ISA_EXT_DATA(sscsrind, RISCV_ISA_EXT_SSCSRIND),
-- 
2.34.1