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Message-ID: <20240218200112.GK7120@pendragon.ideasonboard.com>
Date: Sun, 18 Feb 2024 22:01:12 +0200
From: Laurent Pinchart <laurent.pinchart@...asonboard.com>
To: Alexander Stein <alexander.stein@...tq-group.com>
Cc: linux-media@...r.kernel.org, linux-rockchip@...ts.infradead.org,
devicetree@...r.kernel.org,
Paul Elder <paul.elder@...asonboard.com>,
kieran.bingham@...asonboard.com, tomi.valkeinen@...asonboard.com,
umang.jain@...asonboard.com, aford173@...il.com,
Dafna Hirschfeld <dafna@...tmail.com>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Heiko Stuebner <heiko@...ech.de>,
"moderated list:ARM/Rockchip SoC support" <linux-arm-kernel@...ts.infradead.org>,
open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v12 11/12] media: rkisp1: Fix endianness on raw streams
on i.MX8MP
On Fri, Feb 16, 2024 at 11:28:36AM +0100, Alexander Stein wrote:
> Hi Paul,
>
> thanks for updating this.
>
> Am Freitag, 16. Februar 2024, 10:54:57 CET schrieb Paul Elder:
> > The i.MX8MP has extra register fields in the memory interface control
> > register for setting the output format, which work with the output
> > alignment format register for byte-swapping and LSB/MSB alignment.
> >
> > With processed and 8-bit raw streams, it doesn't cause any problems to
> > not set these, but with raw streams of higher bit depth the endianness
> > is swapped and the data is not aligned properly.
> >
> > Add support for settings these registers and plumb them in to fix this.
s/settings/setting/
> >
> > Signed-off-by: Paul Elder <paul.elder@...asonboard.com>
> > ---
> > Changes in v12:
> > - replace MP_OUTPUT_FORMAT feature flag with MAIN_STRIDE
> >
> > New in v6
> > ---
> > .../platform/rockchip/rkisp1/rkisp1-capture.c | 93 ++++++++++++++-----
> > .../platform/rockchip/rkisp1/rkisp1-regs.h | 8 ++
> > 2 files changed, 78 insertions(+), 23 deletions(-)
> >
> > diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
> > b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c index
> > 64b1d1104e20..28a99b31581b 100644
> > --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
> > +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
> > @@ -48,16 +48,20 @@ enum rkisp1_plane {
> > * @fmt_type: helper filed for pixel format
> > * @uv_swap: if cb cr swapped, for yuv
> > * @yc_swap: if y and cb/cr swapped, for yuv
> > + * @byte_swap: if byte pairs are swapped, for raw
> > * @write_format: defines how YCbCr self picture data is written to memory
> > - * @output_format: defines sp output format
> > + * @output_format_mp: defines mp output format
> > + * @output_format_sp: defines sp output format
I don't see any format that defines both output_format_mp and
output_format_sp. Unless you want to merge the rkisp1_mp_fmts and
rkisp1_sp_fmts arrays (I'm not sure it would be doable), you could use a
single output_format field. Only the description needs to be updated.
> > * @mbus: the mbus code on the src resizer pad that matches the pixel
> > format */
> > struct rkisp1_capture_fmt_cfg {
> > u32 fourcc;
> > u32 uv_swap : 1;
> > u32 yc_swap : 1;
> > + u32 byte_swap : 1;
> > u32 write_format;
> > - u32 output_format;
> > + u32 output_format_mp;
> > + u32 output_format_sp;
> > u32 mbus;
> > };
> >
> > @@ -96,42 +100,50 @@ static const struct rkisp1_capture_fmt_cfg
> > rkisp1_mp_fmts[] = { .fourcc = V4L2_PIX_FMT_YUYV,
> > .uv_swap = 0,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUVINT,
> > + .output_format_mp = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
> > .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_UYVY,
> > .uv_swap = 0,
> > .yc_swap = 1,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUVINT,
> > + .output_format_mp = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
> > .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_YUV422P,
> > .uv_swap = 0,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> > + .output_format_mp = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
> > .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_NV16,
> > .uv_swap = 0,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
> > + .output_format_mp = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
> > .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_NV61,
> > .uv_swap = 1,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
> > + .output_format_mp = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
> > .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_NV16M,
> > .uv_swap = 0,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
> > + .output_format_mp = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
> > .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_NV61M,
> > .uv_swap = 1,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
> > + .output_format_mp = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
> > .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_YVU422M,
> > .uv_swap = 1,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> > + .output_format_mp = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422,
> > .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> > },
> > /* yuv400 */
> > @@ -139,6 +151,7 @@ static const struct rkisp1_capture_fmt_cfg
> > rkisp1_mp_fmts[] = { .fourcc = V4L2_PIX_FMT_GREY,
> > .uv_swap = 0,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> > + .output_format_mp = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV400,
> > .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> > },
> > /* yuv420 */
> > @@ -146,81 +159,107 @@ static const struct rkisp1_capture_fmt_cfg
> > rkisp1_mp_fmts[] = { .fourcc = V4L2_PIX_FMT_NV21,
> > .uv_swap = 1,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
> > + .output_format_mp = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
> > .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_NV12,
> > .uv_swap = 0,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
> > + .output_format_mp = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
> > .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_NV21M,
> > .uv_swap = 1,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
> > + .output_format_mp = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
> > .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_NV12M,
> > .uv_swap = 0,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
> > + .output_format_mp = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
> > .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_YUV420,
> > .uv_swap = 0,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> > + .output_format_mp = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
> > .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_YVU420,
> > .uv_swap = 1,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> > + .output_format_mp = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420,
> > .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
> > },
> > /* raw */
> > {
> > .fourcc = V4L2_PIX_FMT_SRGGB8,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> > + .output_format_mp = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8,
> > .mbus = MEDIA_BUS_FMT_SRGGB8_1X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_SGRBG8,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> > + .output_format_mp = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8,
> > .mbus = MEDIA_BUS_FMT_SGRBG8_1X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_SGBRG8,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> > + .output_format_mp = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8,
> > .mbus = MEDIA_BUS_FMT_SGBRG8_1X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_SBGGR8,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
> > + .output_format_mp = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8,
> > .mbus = MEDIA_BUS_FMT_SBGGR8_1X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_SRGGB10,
> > + .byte_swap = 1,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
> > + .output_format_mp = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10,
> > .mbus = MEDIA_BUS_FMT_SRGGB10_1X10,
> > }, {
> > .fourcc = V4L2_PIX_FMT_SGRBG10,
> > + .byte_swap = 1,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
> > + .output_format_mp = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10,
> > .mbus = MEDIA_BUS_FMT_SGRBG10_1X10,
> > }, {
> > .fourcc = V4L2_PIX_FMT_SGBRG10,
> > + .byte_swap = 1,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
> > + .output_format_mp = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10,
> > .mbus = MEDIA_BUS_FMT_SGBRG10_1X10,
> > }, {
> > .fourcc = V4L2_PIX_FMT_SBGGR10,
> > + .byte_swap = 1,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
> > + .output_format_mp = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10,
> > .mbus = MEDIA_BUS_FMT_SBGGR10_1X10,
> > }, {
> > .fourcc = V4L2_PIX_FMT_SRGGB12,
> > + .byte_swap = 1,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
> > + .output_format_mp = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12,
> > .mbus = MEDIA_BUS_FMT_SRGGB12_1X12,
> > }, {
> > .fourcc = V4L2_PIX_FMT_SGRBG12,
> > + .byte_swap = 1,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
> > + .output_format_mp = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12,
> > .mbus = MEDIA_BUS_FMT_SGRBG12_1X12,
> > }, {
> > .fourcc = V4L2_PIX_FMT_SGBRG12,
> > + .byte_swap = 1,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
> > + .output_format_mp = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12,
> > .mbus = MEDIA_BUS_FMT_SGBRG12_1X12,
> > }, {
> > .fourcc = V4L2_PIX_FMT_SBGGR12,
> > + .byte_swap = 1,
> > .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
> > + .output_format_mp = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12,
> > .mbus = MEDIA_BUS_FMT_SBGGR12_1X12,
> > },
> > };
> > @@ -235,50 +274,50 @@ static const struct rkisp1_capture_fmt_cfg
> > rkisp1_sp_fmts[] = { .fourcc = V4L2_PIX_FMT_YUYV,
> > .uv_swap = 0,
> > .write_format = RKISP1_MI_CTRL_SP_WRITE_INT,
> > - .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
> > + .output_format_sp = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
> > .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_UYVY,
> > .uv_swap = 0,
> > .yc_swap = 1,
> > .write_format = RKISP1_MI_CTRL_SP_WRITE_INT,
> > - .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
> > + .output_format_sp = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
> > .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_YUV422P,
> > .uv_swap = 0,
> > .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
> > - .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
> > + .output_format_sp = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
> > .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_NV16,
> > .uv_swap = 0,
> > .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
> > - .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
> > + .output_format_sp = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
> > .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_NV61,
> > .uv_swap = 1,
> > .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
> > - .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
> > + .output_format_sp = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
> > .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_NV16M,
> > .uv_swap = 0,
> > .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
> > - .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
> > + .output_format_sp = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
> > .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_NV61M,
> > .uv_swap = 1,
> > .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
> > - .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
> > + .output_format_sp = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
> > .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_YVU422M,
> > .uv_swap = 1,
> > .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
> > - .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
> > + .output_format_sp = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
> > .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> > },
> > /* yuv400 */
> > @@ -286,19 +325,19 @@ static const struct rkisp1_capture_fmt_cfg
> > rkisp1_sp_fmts[] = { .fourcc = V4L2_PIX_FMT_GREY,
> > .uv_swap = 0,
> > .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
> > - .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
> > + .output_format_sp = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
> > .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> > },
> > /* rgb */
> > {
> > .fourcc = V4L2_PIX_FMT_XBGR32,
> > .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
> > - .output_format = RKISP1_MI_CTRL_SP_OUTPUT_RGB888,
> > + .output_format_sp = RKISP1_MI_CTRL_SP_OUTPUT_RGB888,
> > .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_RGB565,
> > .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
> > - .output_format = RKISP1_MI_CTRL_SP_OUTPUT_RGB565,
> > + .output_format_sp = RKISP1_MI_CTRL_SP_OUTPUT_RGB565,
> > .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
> > },
> > /* yuv420 */
> > @@ -306,37 +345,37 @@ static const struct rkisp1_capture_fmt_cfg
> > rkisp1_sp_fmts[] = { .fourcc = V4L2_PIX_FMT_NV21,
> > .uv_swap = 1,
> > .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
> > - .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
> > + .output_format_sp = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
> > .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_NV12,
> > .uv_swap = 0,
> > .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
> > - .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
> > + .output_format_sp = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
> > .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_NV21M,
> > .uv_swap = 1,
> > .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
> > - .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
> > + .output_format_sp = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
> > .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_NV12M,
> > .uv_swap = 0,
> > .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
> > - .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
> > + .output_format_sp = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
> > .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_YUV420,
> > .uv_swap = 0,
> > .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
> > - .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
> > + .output_format_sp = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
> > .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
> > }, {
> > .fourcc = V4L2_PIX_FMT_YVU420,
> > .uv_swap = 1,
> > .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
> > - .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
> > + .output_format_sp = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
> > .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
> > },
> > };
> > @@ -484,10 +523,12 @@ static void rkisp1_mp_config(struct rkisp1_capture
> > *cap) */
> > if (rkisp1_has_feature(rkisp1, MAIN_STRIDE)) {
> > reg = rkisp1_read(rkisp1,
> RKISP1_CIF_MI_OUTPUT_ALIGN_FORMAT);
> > - if (cap->pix.cfg->yc_swap)
> > + if (cap->pix.cfg->yc_swap || cap->pix.cfg->byte_swap)
> > reg |=
> RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_BYTE_SWAP_BYTES;
> > else
> > reg &=
> ~RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_BYTE_SWAP_BYTES;
> > +
> > + reg |= RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_LSB_ALIGNMENT;
> > rkisp1_write(rkisp1, RKISP1_CIF_MI_OUTPUT_ALIGN_FORMAT,
> reg);
> > }
> >
> > @@ -554,7 +595,7 @@ static void rkisp1_sp_config(struct rkisp1_capture *cap)
> > mi_ctrl &= ~RKISP1_MI_CTRL_SP_FMT_MASK;
> > mi_ctrl |= cap->pix.cfg->write_format |
> > RKISP1_MI_CTRL_SP_INPUT_YUV422 |
> > - cap->pix.cfg->output_format |
> > + cap->pix.cfg->output_format_sp |
> > RKISP1_CIF_MI_SP_AUTOUPDATE_ENABLE;
> > rkisp1_write(rkisp1, RKISP1_CIF_MI_CTRL, mi_ctrl);
> > }
> > @@ -946,6 +987,7 @@ static void rkisp1_cap_stream_enable(struct
> > rkisp1_capture *cap) struct rkisp1_device *rkisp1 = cap->rkisp1;
> > struct rkisp1_capture *other = &rkisp1->capture_devs[cap->id ^ 1];
> > bool has_self_path = rkisp1_has_feature(rkisp1, SELF_PATH);
> > + u32 reg;
> >
> > cap->ops->set_data_path(cap);
> > cap->ops->config(cap);
> > @@ -965,8 +1007,13 @@ static void rkisp1_cap_stream_enable(struct
> > rkisp1_capture *cap) */
> > if (!has_self_path || !other->is_streaming) {
> > /* force cfg update */
> > - rkisp1_write(rkisp1, RKISP1_CIF_MI_INIT,
> > - RKISP1_CIF_MI_INIT_SOFT_UPD);
> > + reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_INIT);
> > +
> > + if (rkisp1_has_feature(rkisp1, MAIN_STRIDE))
> > + reg |= cap->pix.cfg->output_format_mp;
>
> I don't have any documents regarding that ISP, but shouldn't you clear the
> bits for output_format_mp before OR'ing the new ones on top?
I think it would be even better to set the output format in
rkisp1_mp_config(), writing the whole register there.
> > +
> > + reg |= RKISP1_CIF_MI_INIT_SOFT_UPD;
> > + rkisp1_write(rkisp1, RKISP1_CIF_MI_INIT, reg);
> > rkisp1_set_next_buf(cap);
> > }
> > spin_unlock_irq(&cap->buf.lock);
> > diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
> > b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h index
> > 3b19c8411360..762243016f05 100644
> > --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
> > +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
> > @@ -144,6 +144,14 @@
> > /* MI_INIT */
> > #define RKISP1_CIF_MI_INIT_SKIP BIT(2)
> > #define RKISP1_CIF_MI_INIT_SOFT_UPD BIT(4)
> > +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV400 (0 << 5)
> > +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420 (1 << 5)
> > +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422 (2 << 5)
> > +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV444 (3 << 5)
> > +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12 (4 << 5)
> > +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8 (5 << 5)
> > +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_JPEG (6 << 5)
> > +#define RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10 (7 << 5)
> >
> > /* MI_CTRL_SHD */
> > #define RKISP1_CIF_MI_CTRL_SHD_MP_IN_ENABLED BIT(0)
--
Regards,
Laurent Pinchart
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