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Message-ID: <tencent_594131AD216D8DE97CCC8265DA5D8E45B808@qq.com>
Date: Tue, 20 Feb 2024 00:32:09 +0800
From: Yangyu Chen <cyy@...self.name>
To: linux-riscv@...ts.infradead.org
Cc: Jisheng Zhang <jszhang@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Guo Ren <guoren@...nel.org>,
Alexandre Ghiti <alexghiti@...osinc.com>,
linux-kernel@...r.kernel.org,
Yangyu Chen <cyy@...self.name>
Subject: [PATCH] riscv: mm: fix NOCACHE_THEAD does not set bit[61] correctly
Previous commit dbfbda3bd6bf("riscv: mm: update T-Head memory type
definitions") missed a `<` for bit shifting, result in bit[61] does not set
in _PAGE_NOCACHE_THEAD and leaves bit[0] set instead. This patch get this
fixed.
Link: https://lore.kernel.org/linux-riscv/20230912072510.2510-1-jszhang@kernel.org/ [1]
Signed-off-by: Yangyu Chen <cyy@...self.name>
---
arch/riscv/include/asm/pgtable-64.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
index b42017d76924..b99bd66107a6 100644
--- a/arch/riscv/include/asm/pgtable-64.h
+++ b/arch/riscv/include/asm/pgtable-64.h
@@ -136,7 +136,7 @@ enum napot_cont_order {
* 10010 - IO Strongly-ordered, Non-cacheable, Non-bufferable, Shareable, Non-trustable
*/
#define _PAGE_PMA_THEAD ((1UL << 62) | (1UL << 61) | (1UL << 60))
-#define _PAGE_NOCACHE_THEAD ((1UL < 61) | (1UL << 60))
+#define _PAGE_NOCACHE_THEAD ((1UL << 61) | (1UL << 60))
#define _PAGE_IO_THEAD ((1UL << 63) | (1UL << 60))
#define _PAGE_MTMASK_THEAD (_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL << 59))
--
2.43.0
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