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Message-ID: <6ec0f73f-cbac-44c5-a215-d3754ce6a5d8@sirena.org.uk>
Date: Mon, 19 Feb 2024 13:42:29 +0000
From: Mark Brown <broonie@...nel.org>
To: Anshuman Khandual <anshuman.khandual@....com>
Cc: linux-arm-kernel@...ts.infradead.org,
	Catalin Marinas <catalin.marinas@....com>,
	Will Deacon <will@...nel.org>, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] arm64/sysreg: Add register fields for ID_AA64DFR1_EL1

On Sun, Feb 18, 2024 at 06:04:34AM +0530, Anshuman Khandual wrote:

> Just wondering - would something like the following make sense. Because
> 0b0000 signifies that the cycle counter would just ignore PMCR_EL0.FZS,
> where as it gets frozen with 0b0001.

> UnsignedEnum   55:52   DPFZS
>        0b0000  IGNR
>        0b0001  FRZN
> EndEnum

LGTM.

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