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Message-ID: <ZdNvsdao8jbB/52L@lizhi-Precision-Tower-5810>
Date: Mon, 19 Feb 2024 10:11:45 -0500
From: Frank Li <Frank.li@....com>
To: lpieralisi@...nel.org
Cc: bhelgaas@...gle.com, conor+dt@...nel.org, devicetree@...r.kernel.org,
festevam@...il.com, helgaas@...nel.org, hongxing.zhu@....com,
imx@...ts.linux.dev, kernel@...gutronix.de,
krzysztof.kozlowski+dt@...aro.org, krzysztof.kozlowski@...aro.org,
kw@...ux.com, l.stach@...gutronix.de,
linux-arm-kernel@...ts.infradead.org, linux-imx@....com,
linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
manivannan.sadhasivam@...aro.org, robh@...nel.org,
s.hauer@...gutronix.de, shawnguo@...nel.org
Subject: Re: [PATCH v10 00/14] PCI: imx6: Clean up and add imx95 pci support
On Mon, Feb 05, 2024 at 12:33:21PM -0500, Frank Li wrote:
> first 6 patches use drvdata: flags to simplify some switch-case code.
> Improve maintaince and easy to read code.
>
@Lorenzo Pieralisi:
Do you have chance to look other patches?
Mani's apply EP side change.
'PCI: imx6: Add iMX95 Endpoint (EP) support' need be rebased.
Frank
> Then add imx95 basic pci host function.
>
> follow two patch do endpoint code clean up.
> Then add imx95 basic endpont function.
>
> Compared with v2, added EP function support and some fixes, please change
> notes at each patches.
>
> Change from v9 to v10
> - remove two patches:
> > dt-bindings: imx6q-pcie: Add linux,pci-domain as required for iMX8MQ
> > PCI: imx6: Using "linux,pci-domain" as slot ID
> it is not good solution to fixed hardcode check to get controller id.
> Will see better solution later.
>
> dt-binding pass pcie node:
>
> pcie0: pcie@...00000 {
> compatible = "fsl,imx95-pcie";
> reg = <0 0x4c300000 0 0x40000>,
> <0 0x4c360000 0 0x10000>,
> <0 0x4c340000 0 0x20000>,
> <0 0x60100000 0 0xfe00000>;
> reg-names = "dbi", "atu", "app", "config";
> #address-cells = <3>;
> #size-cells = <2>;
> device_type = "pci";
> linux,pci-domain = <0>;
> bus-range = <0x00 0xff>;
> ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>,
> <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>;
> num-lanes = <1>;
> num-viewport = <8>;
> interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "msi";
> #interrupt-cells = <1>;
> interrupt-map-mask = <0 0 0 0x7>;
> interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
> <0 0 0 2 &gic 0 0 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
> <0 0 0 3 &gic 0 0 GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
> <0 0 0 4 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
> fsl,max-link-speed = <3>;
> clocks = <&scmi_clk IMX95_CLK_HSIO>,
> <&scmi_clk IMX95_CLK_HSIOPLL>,
> <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
> assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> <&scmi_clk IMX95_CLK_HSIOPLL>,
> <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
> assigned-clock-parents = <0>, <0>,
> <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
> power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
> /* 0x30~0x37 stream id for pci0 */
> /*
> * iommu-map = <0x000 &apps_smmu 0x30 0x1>,
> * <0x100 &apps_smmu 0x31 0x1>;
> */
> status = "disabled";
> };
>
> pcie1: pcie-ep@...80000 {
> compatible = "fsl,imx95-pcie-ep";
> reg = <0 0x4c380000 0 0x20000>,
> <0 0x4c3e0000 0 0x1000>,
> <0 0x4c3a0000 0 0x1000>,
> <0 0x4c3c0000 0 0x10000>,
> <0 0x4c3f0000 0 0x10000>,
> <0xa 0 1 0>;
> reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space";
> interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "dma";
> fsl,max-link-speed = <3>;
> clocks = <&scmi_clk IMX95_CLK_HSIO>,
> <&scmi_clk IMX95_CLK_HSIOPLL>,
> <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
> assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
> <&scmi_clk IMX95_CLK_HSIOPLL>,
> <&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
> assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
> assigned-clock-parents = <0>, <0>,
> <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
> power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
> status = "disabled";
> };
>
> Frank Li (13):
> PCI: imx6: Simplify clock handling by using clk_bulk*() function
> PCI: imx6: Simplify phy handling by using IMX6_PCIE_FLAG_HAS_PHYDRV
> PCI: imx6: Simplify reset handling by using by using
> *_FLAG_HAS_*_RESET
> PCI: imx6: Simplify ltssm_enable() by using ltssm_off and ltssm_mask
> PCI: imx6: Simplify configure_type() by using mode_off and mode_mask
> PCI: imx6: Simplify switch-case logic by involve init_phy callback
> dt-bindings: imx6q-pcie: Clean up irrationality clocks check
> dt-bindings: imx6q-pcie: Restruct reg and reg-name
> PCI: imx6: Add iMX95 PCIe Root Complex support
> PCI: imx6: Clean up get addr_space code
> PCI: imx6: Add epc_features in imx6_pcie_drvdata
> dt-bindings: imx6q-pcie: Add iMX95 pcie endpoint compatible string
> PCI: imx6: Add iMX95 Endpoint (EP) support
>
> Richard Zhu (1):
> dt-bindings: imx6q-pcie: Add imx95 pcie compatible string
>
> .../bindings/pci/fsl,imx6q-pcie-common.yaml | 17 +-
> .../bindings/pci/fsl,imx6q-pcie-ep.yaml | 46 +-
> .../bindings/pci/fsl,imx6q-pcie.yaml | 49 +-
> drivers/pci/controller/dwc/pci-imx6.c | 634 ++++++++++--------
> 4 files changed, 436 insertions(+), 310 deletions(-)
>
> --
> 2.34.1
>
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