| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <ZdUQBl5pkFg2i1iu@mehdi-archlinux> Date: Tue, 20 Feb 2024 21:48:06 +0100 From: Mehdi Djait <mehdi.djait.k@...il.com> To: Sakari Ailus <sakari.ailus@....fi> Cc: mchehab@...nel.org, heiko@...ech.de, hverkuil-cisco@...all.nl, krzysztof.kozlowski+dt@...aro.org, robh+dt@...nel.org, conor+dt@...nel.org, linux-media@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, thomas.petazzoni@...tlin.com, alexandre.belloni@...tlin.com, maxime.chevallier@...tlin.com, paul.kocialkowski@...tlin.com, michael.riesch@...fvision.net, laurent.pinchart@...asonboard.com, Mehdi Djait <mehdi.djait@...tlin.com>, Conor Dooley <conor.dooley@...rochip.com> Subject: Re: [RESEND Patch v13 1/3] media: dt-bindings: media: add bindings for Rockchip CIF Hi Sakari, On Tue, Feb 20, 2024 at 07:30:53PM +0000, Sakari Ailus wrote: > Hi Mehdi, > > On Tue, Feb 20, 2024 at 06:04:10PM +0100, Mehdi Djait wrote: > > Hi Sakari, > > > > Thank you for the review. > > You're welcome! > > > > > On Tue, Feb 13, 2024 at 12:04:58PM +0000, Sakari Ailus wrote: > > > Hi Mehdi, > > > > > > Thanks for the patchset. > > > > > > On Sun, Feb 11, 2024 at 08:03:30PM +0100, Mehdi Djait wrote: > > > > From: Mehdi Djait <mehdi.djait@...tlin.com> > > > > > > > > Add a documentation for the Rockchip Camera Interface binding. > > > > > > > > Reviewed-by: Conor Dooley <conor.dooley@...rochip.com> > > > > Reviewed-by: Michael Riesch <michael.riesch@...fvision.net> > > > > Signed-off-by: Mehdi Djait <mehdi.djait@...tlin.com> > > > > Signed-off-by: Mehdi Djait <mehdi.djait.k@...il.com> > > > > --- > > > > .../bindings/media/rockchip,px30-vip.yaml | 123 ++++++++++++++++++ > > > > 1 file changed, 123 insertions(+) > > > > create mode 100644 Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml > > > > > > > > diff --git a/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml b/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml > > > > new file mode 100644 > > > > index 000000000000..6af4a9b6774a > > > > --- /dev/null > > > > +++ b/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml > > > > @@ -0,0 +1,123 @@ > > > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > > > +%YAML 1.2 > > > > +--- > > > > +$id: http://devicetree.org/schemas/media/rockchip,px30-vip.yaml# > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > > + > > > > +title: Rockchip Camera Interface (CIF) > > > > + > > > > +maintainers: > > > > + - Mehdi Djait <mehdi.djait@...tlin.com> > > > > + > > > > +description: > > > > + CIF is a camera interface present on some Rockchip SoCs. It receives the data > > > > + from Camera sensor or CCIR656 encoder and transfers it into system main memory > > > > + by AXI bus. > > > > + > > > > +properties: > > > > + compatible: > > > > + const: rockchip,px30-vip > > > > + > > > > + reg: > > > > + maxItems: 1 > > > > + > > > > + interrupts: > > > > + maxItems: 1 > > > > + > > > > + clocks: > > > > + items: > > > > + - description: ACLK > > > > + - description: HCLK > > > > + - description: PCLK > > > > + > > > > + clock-names: > > > > + items: > > > > + - const: aclk > > > > + - const: hclk > > > > + - const: pclk > > > > + > > > > + resets: > > > > + items: > > > > + - description: AXI > > > > + - description: AHB > > > > + - description: PCLK IN > > > > + > > > > + reset-names: > > > > + items: > > > > + - const: axi > > > > + - const: ahb > > > > + - const: pclkin > > > > + > > > > + power-domains: > > > > + maxItems: 1 > > > > + > > > > + ports: > > > > + $ref: /schemas/graph.yaml#/properties/ports > > > > + > > > > + properties: > > > > + port@0: > > > > + $ref: /schemas/graph.yaml#/$defs/port-base > > > > + unevaluatedProperties: false > > > > + description: input port on the parallel interface > > > > + > > > > + properties: > > > > + endpoint: > > > > + $ref: video-interfaces.yaml# > > > > + unevaluatedProperties: false > > > > + > > > > + properties: > > > > + bus-type: > > > > + enum: [5, 6] > > > > + > > > > + required: > > > > + - bus-type > > > > > > What about the vsync-active, hsync-active and data-active properties? > > > Aren't they relevant for this device? Are there default values? This should > > > be part of the bindings for the device, shouldn't it? > > > > > > > From what I gathered from the Rockchip PX30 TRM and the other > > available documents from Rockchip, I will add the following: > > > > diff --git a/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml b/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml > > index 6af4a9b6774a..6920b0cb0507 100644 > > --- a/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml > > +++ b/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml > > @@ -69,6 +69,14 @@ properties: > > bus-type: > > enum: [5, 6] > > > > + hsync-active: > > + enum: [0, 1] > > + default: 1 > > + > > + vsync-active: > > + enum: [0, 1] > > + default: 0 > > I'd use the same default for both, whether it's 0 or 1. > Is this supposed to be the default value HIGH or LOW if it is not configured by the driver ? because the manual states the following: HREF_POL Href input polarity: 1'b0 : high active 1'b1 : low active RESET VALUE: 0x0 VSYNC_POL Vsync input polarity: 1'b0 : low active 1'b1 : high active RESET VALUE: 0x0 And that's why I chose 1 for hsync and 0 for vsync -- Kind Regards Mehdi Djait
Powered by blists - more mailing lists