linux-kernel - Re: [PATCH] arm64: ls1046ardb: Replace XGMII with 10GBASE-R phy mode

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Date: Wed, 21 Feb 2024 01:06:56 +0200
From: Vladimir Oltean <vladimir.oltean@....com>
To: Sean Anderson <sean.anderson@...o.com>
Cc: zachary.goldstein@...current-rt.com, Shawn Guo <shawnguo@...nel.org>,
	Madalin Bucur <madalin.bucur@....com>, Li Yang <leoyang.li@....com>,
	Rob Herring <robh+dt@...nel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
	Conor Dooley <conor+dt@...nel.org>, Andrew Lunn <andrew@...n.ch>,
	Heiner Kallweit <hkallweit1@...il.com>,
	Russell King <linux@...linux.org.uk>,
	"David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org, netdev@...r.kernel.org
Subject: Re: [PATCH] arm64: ls1046ardb: Replace XGMII with 10GBASE-R phy mode

On Tue, Feb 20, 2024 at 05:52:36PM -0500, Sean Anderson wrote:
> With SGMII and XFI, the PCS sits on the MAC's MDIO bus. So for SGMII and
> XFI if we don't have any labels we can just assume the PCS handle is for
> the right PCS. But for QSGMII the PCSs sit on another MAC's MDIO bus. So
> we need to tell the MAC where to find the PCS. This means we need to
> supply multiple PCSs to the MAC

So how did the other Layerscape devices with the same SerDes, PCS and
mEMAC manage to get by and support QSGMII without listing all possible
PCSes in pcs-handle-names? :-/ DPAA2 has the exact same situation with
the QSGMII PCS situated on the internal bus of another DPMAC.

It is unnecessary and buggy complexity, and it will only have to become
worse when I add support for C73 backplane autoneg in lynx-pcs and the
fman_memac driver, because I will need yet another PCS handle, this time
not even one that represents a phy-mode in particular, but a PCS handle
for C73 (with C73, the autoneg process determines the dynamic phy-mode).