linux-kernel - 回复: 回复: [PATCH v2 2/2] irqchip: Add StarFive external interrupt controller

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Message-ID:
 <SHXPR01MB06719FB406FAA201595028A8F250A@SHXPR01MB0671.CHNPR01.prod.partner.outlook.cn>
Date: Tue, 20 Feb 2024 09:39:14 +0000
From: Changhuang Liang <changhuang.liang@...rfivetech.com>
To: Thomas Gleixner <tglx@...utronix.de>, Rob Herring <robh+dt@...nel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Conor Dooley
	<conor+dt@...nel.org>, Philipp Zabel <p.zabel@...gutronix.de>
CC: Leyfoon Tan <leyfoon.tan@...rfivetech.com>, Jack Zhu
	<jack.zhu@...rfivetech.com>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>, "devicetree@...r.kernel.org"
	<devicetree@...r.kernel.org>
Subject:
 回复: 回复: [PATCH v2 2/2] irqchip: Add StarFive external interrupt controller

Hi, Thomas

> -----邮件原件-----
> 发件人: Thomas Gleixner <tglx@...utronix.de>
> 发送时间: 2024年2月20日 17:28
> 收件人: Changhuang Liang <changhuang.liang@...rfivetech.com>; Rob
> Herring <robh+dt@...nel.org>; Krzysztof Kozlowski
> <krzysztof.kozlowski+dt@...aro.org>; Conor Dooley <conor+dt@...nel.org>;
> Philipp Zabel <p.zabel@...gutronix.de>
> 抄送: Leyfoon Tan <leyfoon.tan@...rfivetech.com>; Jack Zhu
> <jack.zhu@...rfivetech.com>; linux-kernel@...r.kernel.org;
> devicetree@...r.kernel.org
> 主题: Re: 回复: [PATCH v2 2/2] irqchip: Add StarFive external interrupt
> controller
> 
> On Sun, Feb 18 2024 at 02:36, Changhuang Liang wrote:
> >> On Mon, Jan 29 2024 at 21:58, Changhuang Liang wrote:
> > [...]
> >> > +static void starfive_intc_mod(struct starfive_irq_chip *irqc, u32
> >> > +reg, u32 mask, u32 data) {
> >> > +	u32 value;
> >> > +
> >> > +	value = ioread32(irqc->base + reg) & ~mask;
> >> > +	data &= mask;
> >>
> >> Why?
> >>
> >
> > If I want to update the reg  GENMASK(7, 4)  to value 5, the data I
> > will pass in 5 << 4
> 
> All call sites pass a single bit to set/clear, right? So this GENMASK argument
> does not make sense at all.
> 

Yes, I will update this function